8.4.6.1 IO Switching Control

The card interface IOs (IOUC, IOS1, IOS2 and IOS3) connect to the IOMC1 and IOMC2 through switches inside the TCA5013.

The IOUC pin is connected to IOMC1 through an SPST (single-pole single-throw) switch. The switch is controlled by the IO_EN_UC bit (Reg 0x01, Bit 5).The IO_EN_UC bit shall be set to 1 before card activation is started to ensure that the host processor is able to receive the ATR response from the smartcard. When an I2C command is received to open or close the switch, it is immediately implemented regardless of the status of IOUC or IOMC1 pins. It is therefore possible that the switch opens or closes during a rising or falling edge, which could result in a glitch on the IOUC or IOMC1 pins.

The IOS1, IOS2 and IOS3 all are connected to IOMC2 through a SP3T (single-pole triple-throw) switch, such that only one of the SAM interfaces can be connected to IOMC2 at any one time. The connection between the IOMC2 and the SAM card IO pins is controlled by IO_EN_S1 (Reg 0x11, Bit 5), IO_EN_S2 (Reg 0x21, Bit 5), IO_EN_S3 (Reg 0x31, Bit 5). If any one of the IO_EN bits is set for example, if SAM1 is initially connected by setting IO_EN of the SAM1 interface settings register to 1. When the IO_EN bit of the SAM2 or SAM3 is set to 1, the SAM1 gets disconnected and its IO_EN bit will be set to 0. Only one SAM can be connected to the IOUC2 at one time and whenever the IO_EN bit of any SAM interface settings register is set to 1, all other IO_EN bits get cleared (set to 0). Similar to the user card, the SAM IO mux can also result in a short duration pulse, if IOUC2 is not in the same state as the SAMs being switched to/from. Also when making the switch, the TCA5013 uses a break –before-make switch topology in order to avoid any glitches on the lines due to the switching itself.