8.4.9.6 MUTE Fault

In Asynchronous Operating Mode when the ATR response from the smartcard is received after the ‘ATR valid window’ (refer to Figure 6) the MUTE bit (bit [5]) of card interface status register (Reg 0x00 for user card, Reg 0x10 for SAM1, Reg 0x20 for SAM2 and Reg 0x30 for SAM3) is set and the INT pin is asserted low. The interrupt bit corresponding to the card interface in the interrupt status register (Reg 0x41) is also set. The interrupt bit is cleared and the INT pin is released, when the interrupt status register is read. The EARLY bit is cleared only when the corresponding card interface status register is read.