8.5.1 I²C Interface Operation

The device has a standard bidirectional I²C that is used by the microcontroller to access the device Register Maps that is used to configure the device and read the status of various fault flags in the device. The interface consists of the serial clock (SCL) and serial data (SDA) lines and is capable of MHz operation. Both SDA and SCL must be connected to V_DDI through a pull-up resistor. The size of the pull-up resistor is determined by the amount of capacitance on the I²C lines (for further details refer to I²C standard specification).

I²C communication with this device is initiated by a master (microcontroller) sending a START condition, a high-to-low transition on the SDA input/output, while the SCL input is high. Only one data bit is transferred during each clock pulse. A STOP condition is a low-to-high transition on the SDA input/output while the SCL input is high. A STOP condition shall be sent by the master to indicate to the slave that a particular transaction has been completed. The data on the SDA line must remain stable during the high phase of the clock period, as changes in the data line when SCL is high are interpreted as control commands (START or STOP).

Figure 20 shows the definition of an I²C START condition and Figure 21 shows timing of a bit transfer on the I²C bus. I²C

Figure 20. Definition of Start and Stop Conditions

Figure 21. Bit Transfer

Any number of data bytes can be transferred from the master to slave (TCA5013) between the START and STOP conditions. Each byte of eight bits is followed by one ACK bit. The master must release the SDA line before the slave can send an ACK bit. To send an ACK bit the slave pulls down the SDA line during the low phase of ACK-related clock period, so that the SDA line is stable low during the high phase of the ACK-related clock period. When the slave is addressed, it generates an ACK after each byte is received. The master is not required to generate an ACK after each byte that it receives from the slave transmitter

Figure 22 shows the timing diagram for generation of the ACK bit on the I²C interface of the TCA5013

Figure 22. Acknowledgment on I²C Bus