ZHCSFH3A September   2016  – February 2023 TCA6408A-Q1

PRODUCTION DATA  

  1. 特性
  2. 应用
  3. 说明
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Voltage Translation
      2. 8.3.2 I/O Port
      3. 8.3.3 Interrupt Output ( INT)
      4. 8.3.4 Reset Input ( RESET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset (POR)
      2. 8.4.2 Powered-Up
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Bus Transactions
        1. 8.5.2.1 Writes
        2. 8.5.2.2 Reads
    6. 8.6 Register Map
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 9.2.1.2 Minimizing ICC When I/O is Used to Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Power-On Reset Requirements
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 商标
    3. 10.3 静电放电警告
    4. 10.4 术语表
  11. 11支持资源
  12. 12Mechanical, Packaging, and Orderable Information

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Overview

The bidirectional voltage-level translation in the TCA6408A-Q1 is provided through VCCI. VCCI must be connected to the VCC of the external SCL/SDA lines. This indicates the VCC level of the I2C bus to the TCA6408A-Q1. The voltage level on the P-port of the TCA6408A-Q1 is determined by VCCP.

The TCA6408A-Q1 consists of one 8-bit Configuration (input or output selection), Input, Output, and Polarity Inversion (active high) Register. At power on, the I/Os are configured as inputs. However, the system controller can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding Input or Output Register. The polarity of the Input Port Register can be inverted with the Polarity Inversion Register. All registers can be read by the system controller.

The system controller can reset the TCA6408A-Q1 in the event of a timeout or other improper operation by asserting a low in the RESET input. The power-on reset puts the registers in their default state and initializes the I2C/SMBus state machine. The RESET pin causes the same reset/initialization to occur without depowering the part.

The TCA6408A-Q1 open-drain interrupt ( INT) output is activated when any input state differs from its corresponding Input Port Register state and is used to indicate to the system controller that an input state has changed.

INT can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the I2C bus. Thus, the TCA6408A-Q1 can remain a simple target device.

The device P-port outputs have high-current sink capabilities for directly driving LEDs while consuming low device current.

One hardware pin (ADDR) can be used to program and vary the fixed I2C address and allow up to two devices to share the same I2C bus or SMBus.