ZHCS290G
September 2009 – June 2018
TCA8418
PRODUCTION DATA.
1
特性
2
应用范围
3
说明
Device Images
简化原理图
4
修订历史记录
5
Pin Configuration and Functions
Pin Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
I2C Interface Timing Requirements
6.7
Reset Timing Requirements
6.8
Switching Characteristics
6.9
Keypad Switching Characteristics
6.10
Typical Characteristics
7
Parameter Measurement Information
8
Detailed Description
8.1
Overview
8.2
Functional Block Diagram
8.3
Feature Description
8.3.1
Key Events
8.3.1.1
Key Event Table
8.3.1.2
General Purpose Input (GPI) Events
8.3.1.3
Key Event (FIFO) Reading
8.3.1.4
Key Event Overflow
8.3.2
Keypad Lock/Unlock
8.3.3
Keypad Lock Interrupt Mask Timer
8.3.4
Control-Alt-Delete Support
8.3.5
Interrupt Output
8.3.5.1
50 Micro-second Interrupt Configuration
8.4
Device Functional Modes
8.4.1
Power-On Reset (POR)
8.4.2
Powered (Key Scan Mode)
8.4.2.1
Idle Key Scan Mode
8.4.2.2
Active Key Scan Mode
8.5
Programming
8.5.1
I2C Interface
8.5.2
Bus Transactions
8.5.2.1
Writes
8.5.2.2
Reads
8.6
Register Maps
8.6.1
Device Address
8.6.2
Control Register and Command Byte
8.6.2.1
Configuration Register (Address 0x01)
8.6.2.2
Interrupt Status Register, INT_STAT (Address 0x02)
8.6.2.3
Key Lock and Event Counter Register, KEY_LCK_EC (Address 0x03)
8.6.2.4
Key Event Registers (FIFO), KEY_EVENT_A–J (Address 0x04–0x0D)
8.6.2.5
Keypad Lock1 to Lock2 Timer Register, KP_LCK_TIMER (Address 0x0E)
8.6.2.6
Unlock1 and Unlock2 Registers, UNLOCK1/2 (Address 0x0F-0x10)
8.6.2.7
GPIO Interrupt Status Registers, GPIO_INT_STAT1–3 (Address 0x11–0x13)
8.6.2.8
GPIO Data Status Registers, GPIO_DAT_STAT1–3 (Address 0x14–0x16)
8.6.2.9
GPIO Data Out Registers, GPIO_DAT_OUT1–3 (Address 0x17–0x19)
8.6.2.10
GPIO Interrupt Enable Registers, GPIO_INT_EN1–3 (Address 0x1A–0x1C)
8.6.2.11
Keypad or GPIO Selection Registers, KP_GPIO1–3 (Address 0x1D–0x1F)
8.6.2.12
GPI Event Mode Registers, GPI_EM1–3 (Address 0x20–0x22)
8.6.2.13
GPIO Data Direction Registers, GPIO_DIR1–3 (Address 0x23–0x25)
8.6.2.14
GPIO Edge/Level Detect Registers, GPIO_INT_LVL1–3 (Address 0x26–0x28)
8.6.2.15
Debounce Disable Registers, DEBOUNCE_DIS1–3 (Address 0x29–0x2B)
8.6.2.16
GPIO pull-up Disable Register, GPIO_PULL1–3 (Address 0x2C–0x2E)
8.6.3
CAD Interrupt Errata
8.6.3.1
Description
8.6.3.2
System Impact
8.6.3.3
System Workaround
8.6.4
Overflow Errata
8.6.4.1
Description
8.6.4.2
System Impact
8.6.4.3
System Workaround
9
Application and Implementation
9.1
Application Information
9.1.1
Ghosting Considerations
9.2
Typical Application
9.2.1
Design Requirements
9.2.2
Detailed Design Procedure
9.2.2.1
Designing the Hardware Layout
9.2.2.2
Configuring the Registers
9.2.3
Application Curves
10
Power Supply Recommendations
11
Layout
11.1
Layout Guidelines
11.2
Layout Example
12
器件和文档支持
12.1
接收文档更新通知
12.2
社区资源
12.3
商标
12.4
静电放电警告
12.5
术语表
13
机械、封装和可订购信息
封装选项
机械数据 (封装 | 引脚)
RTW|24
MPQF167C
散热焊盘机械数据 (封装 | 引脚)
RTW|24
QFND062N
订购信息
zhcs290g_oa
zhcs290g_pm
7
Parameter Measurement Information
A.
C
L
includes probe and jig capacitance. t
ocf
is measured with C
L
of 10 pF or 400 pF.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 16.
I
2
C Interface Load Circuit And Voltage Waveforms
A.
C
L
includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤ 30 ns.
C.
All parameters and waveforms are not applicable to all devices.
Figure 17.
Interrupt Load Circuit And Voltage Waveforms
A.
C
L
includes probe and jig capacitance.
B.
t
pv
is measured from 0.7 × V
CC
on SCL to 50% I/O (Pn) output.
C.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤ 30 ns.
D.
The outputs are measured one at a time, with one transition per measurement.
E.
All parameters and waveforms are not applicable to all devices.
Figure 18.
P Port Load Circuit And Timing Waveforms
A.
C
L
includes probe and jig capacitance.
B.
All inputs are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z
O
= 50 Ω, t
r
/t
f
≤ 30 ns.
C.
The outputs are measured one at a time, with one transition per measurement.
D.
I/Os are configured as inputs.
E.
All parameters and waveforms are not applicable to all devices.
Figure 19.
Reset Load Circuits And Voltage Waveforms
千亿体育app官网登录(中国)官方网站IOS/安卓通用版/手机APP
|
米乐app下载官网(中国)|ios|Android/通用版APP最新版
|
米乐|米乐·M6(中国大陆)官方网站
|
千亿体育登陆地址
|
华体会体育(中国)HTH·官方网站
|
千赢qy国际_全站最新版千赢qy国际V6.2.14安卓/IOS下载
|
18新利网v1.2.5|中国官方网站
|
bob电竞真人(中国官网)安卓/ios苹果/电脑版【1.97.95版下载】
|
千亿体育app官方下载(中国)官方网站IOS/安卓/手机APP下载安装
|