It is possible to have multiple buffers in series, but care must be taken when designing a system.

Figure 9-2 Series Buffer Connections

Each buffer adds approximately 60 mV of offset. Maximum offset (V_OFFSET) should be considered. The low level at the signal origination end is dependent upon bus load. The I²C-bus specification requires that a 3 mA current produces no larger than a 0.4 V V_OL. As an example, if the V_OL at the master is 0.1 V, and there are 4 buffers in series (each adding about 60 mV), then the V_OL at the farthest buffer is approximately 0.34 V. This device has a rise time accelerator (RTA) that activates at 0.6 V. With great care, a system with 4 buffers may work, but as the V_OL moves up, it may be possible to trigger the RTA, creating a false edge on the clock.

It is recommended to limit the number of buffers in series to two, and to keep the load light to minimize the offset.

Another special consideration of series connections is the effect on round-trip-delay. This is the sum of propagation delays through the buffers and any effects on rise time. It is possible that fast mode speeds (400 kHz) are not possible due to delays and bus loading.