A typical application is shown in Figure 10-1. In this example, the system controller is running on a 3.3 V I²C bus, and the target is connected to a 1.2 V I²C bus. Both buses run at 400 kHz. Controller devices can be placed on either bus.

The TCA9517-Q1 is 5-V tolerant, so it does not require any additional circuitry to translate between 0.9 V to 5.25 V bus voltages and 2.7 V to 5.25 V bus voltages.

When the A side of the TCA9517-Q1 is pulled low by a driver on the I²C bus, a comparator detects the falling edge when it goes below 0.3 × V_CCA and causes the internal driver on the B-side to turn on, causing the B-side to pull down to about 0.5 V. When the B-side of the TCA9517-Q1 falls, first a CMOS hysteresis-type input detects the falling edge and causes the internal driver on the A side to turn on and pull the A-side pin down to ground. In order to illustrate what would be seen in a typical application, refer to Figure 10-3 and Figure 10-4. If the bus controller in Figure 10-1 were to write to the target through the TCA9517-Q1, waveforms shown in Figure 10-3 would be observed on the A bus. This looks like a normal I²C transmission, except that the high level may be as low as 0.9 V, and the turn on and turn off of the acknowledge signals are slightly delayed.

On the B-side bus of the TCA9517-Q1, the clock and data lines would have a positive offset from ground equal to the V_OL of the TCA9517-Q1. After the eighth clock pulse, the data line is pulled to the V_OL of the target device, which is very close to ground in this example. At the end of the acknowledge, the level rises only to the low level set by the driver in the TCA9517-Q1 for a short delay, while the A-bus side rises above 0.3 × V_CCA and then continues high.