米6体育平台手机版

ZHCSCR8D September 2014 – October 2017 TCA9534

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

DW|16
- MSOI003I
PW|16
- MPDS361A

散热焊盘机械数据 (封装 | 引脚)

DW|16
- QFND313D

订购信息

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the TCA9534 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device goes through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 38 and Figure 39.

Figure 38. V_CC is Lowered Below the P_ORF Threshold, Then Ramped Back Up to V_CC

Table 8 specifies the performance of the power-on reset feature for the TCA9534 for both types of power-on reset.

Table 8. Recommended Supply Sequencing and Ramp Rates⁽¹⁾

PARAMETER			MIN	MAX	UNIT
V_{CC_FT}	Fall rate	See Figure 38	1	2000	ms
V_{CC_RT}	Rise rate	See Figure 38	0.1	2000	ms
V_{CC_TRR}	Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV or when V_CC drops to GND)	See Figure 38	1		μs
V_{CC_GH}	Level that V_CCP can glitch down to, but not cause a functional disruption when V_{CCX_GW} = 1 μs	See Figure 39		1.2	V
V_{CC_MV}	The minimum voltage that V_CC can glitch down to without causing a reset (V_{CC_GH} must not be violated)	See Figure 39	1.5		V
V_{CC_GW}	Glitch width that does not cause a functional disruption when V_{CCX_GH} = 0.5 × V_CCx	See Figure 39		10	μs

(1) All supply sequencing and ramp rate values are measured at T_A = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 39 and Table 8 provide more information on how to measure these specifications.

Figure 39. Glitch Width and Glitch Height

V_POR is critical to the power-on reset. V_PORR is the voltage level at which the reset condition is released and all the registers and the I²C-SMBus state machine are initialized to their default states. The value of V_POR differs based on the V_CC being lowered to or from 0. Figure 40 and Table 8 provide more details on this specification.

Figure 40. V_POR