8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input. The input voltage may be raised above V_CC to a maximum of 5.5 V.

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either V_CC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.

8.3.2 Interrupt Output (INT)

An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the acknowledge (ACK) bit after the rising edge of the SCL signal. Note that the INT is reset at the ACK just before the byte of changed data is sent. Interrupts that occur during the ACK clock pulse can be lost (or be very short) because of the resetting of the interrupt during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.

Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.

The INT output has an open-drain structure and requires pullup resistor to V_CC.

8.4.1 Power-On Reset

When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9534 in a reset condition until V_CC has reached V_PORR. At that point, the reset condition is released and the TCA9534 registers and SMBus/I²C state machine initializes to their default states. After that, V_CC must be lowered to below V_PORF and then back up to the operating voltage for a power-on reset cycle.

8.5.1 I²C Interface

The TCA9534 has a standard bidirectional I²C interface that is controlled by a master device in order to be configured or read the status of this device. Each slave on the I²C bus has a specific device address to differentiate between other slave devices that are on the same I²C bus. Many slave devices require configuration upon startup to set the behavior of the device. This is typically done when the master accesses internal register maps of the slave, which have unique register addresses. A device can have one or multiple registers where data is stored, written, or read. For more information see the Understanding the I²C Bus application report.

The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines must be connected to V_CC through a pullup resistor. The size of the pullup resistor is determined by the amount of capacitance on the I²C lines. For further details, see the I²C Pullup Resistor Calculation application report. Data transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high after a STOP condition.

Figure 24 and Figure 25 show the general procedure for a master to access a slave device:

1. If a master wants to send data to a slave:
   • Master-transmitter sends a START condition and addresses the slave-receiver.
   • Master-transmitter sends data to slave-receiver.
   • Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
   • Master-receiver sends a START condition and addresses the slave-transmitter.
   • Master-receiver sends the requested register to read to slave-transmitter.
   • Master-receiver receives data from the slave-transmitter.
   • Master-receiver terminates the transfer with a STOP condition.

Figure 24. Definition of Start and Stop Conditions

Figure 25. Bit Transfer

Table 1 shows the TCA9534 interface definition.

8.6.1 Device Address

Figure 26 shows the address byte of the TCA9534.

Figure 26. TCA9534 Address

Table 2 shows the TCA9534 address reference.

The last bit of the slave address defines the operation (read or write) to be performed. When it is high (1), a read is selected, while a low (0) selects a write operation.

8.6.2 Control Register and Command Byte

Following the successful Acknowledgment of the address byte, the bus master sends a command byte that is stored in the control register in the TCA9534 (see Figure 27). Two bits of this command byte state the operation (read or write) and the internal register (input, output, polarity inversion or configuration) that is affected. This register can be written or read through the I²C bus. The command byte is sent only during a write transmission.

Once a command byte has been sent, the register that was addressed continues to be accessed by reads until a new command byte has been sent.

Figure 27. Control Register Bits

Table 3 shows the TCA9534 command byte.

8.6.3 Register Descriptions

The Input Port register (register 0) reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the Configuration register. It only acts on read operation. Writes to these registers have no effect. The default value, X, is determined by the externally applied logic level. See Table 4.

Before a read operation, a write transmission is sent with the command byte to indicate to the I²C device that the Input Port register is accessed next.

The Output Port register (register 1) shows the outgoing logic levels of the pins defined as outputs by the Configuration register. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value. See Table 5.

The Polarity Inversion register (register 2) allows polarity inversion of pins defined as inputs by the Configuration register. If a bit in this register is set (written with 1), the corresponding port pin polarity is inverted. If a bit in this register is cleared (written with a 0), the corresponding port pin original polarity is retained. See Table 6.

The Configuration register (register 3) configures the directions of the I/O pins. If a bit in this register is set to 1, the corresponding port pin is enabled as an input with a high-impedance output driver. If a bit in this register is cleared to 0, the corresponding port pin is enabled as an output. See Table 7.

8.6.3.1 Bus Transactions

Data is exchanged between the master and the TCA9534 through write and read commands.

8.6.3.1.1 Writes

To write on the I²C bus, the master sends a START condition on the bus with the address of the slave, as well as the last bit (the R/W bit) set to 0, which signifies a write. After the slave sends the acknowledge bit, the master then sends the register address of the register to which it is designated to write. The slave acknowledges again, letting the master know it is ready. After this, the master starts sending the register data to the slave until the master has sent all the data necessary (which is sometimes only a single byte), and the master terminates the transmission with a STOP condition.

See Table 3 to see list of the internal registers and a description of each one.

Figure 28 shows an example of writing a single byte to a slave register.

Figure 28. Write to Register

Figure 29 shows an example of writing to the output port register.

Figure 29. Write to Output Port Register

Figure 30 shows an example of writing to the configuration or polarity inversion registers.

Figure 30. Write to Configuration or Polarity Inversion Registers

8.6.3.1.2 Reads

Reading from a slave is very similar to writing, but requires some additional steps. To read from a slave, the master must first instruct the slave which register it is designated to read from. This is done by the master starting off the transmission in a similar fashion as the write, by sending the address with the R/W bit equal to 0 (signifying a write), followed by the register address it is designated to read from. When the slave acknowledges this register address, the master sends a START condition again, followed by the slave address with the R/W bit set to 1 (signifying a read). This time, the slave acknowledges the read request, and the master releases the SDA bus but continues supplying the clock to the slave. During this part of the transaction, the master becomes the master-receiver, and the slave becomes the slave-transmitter.

The master continues to send out the clock pulses but releases the SDA line so that the slave can transmit data. At the end of every byte of data, the master sends an ACK to the slave, letting the slave know that it is ready for more data. When the master has received the number of bytes it is expecting, it sends a NACK, signaling to the slave to halt communications and release the bus. The master follows this up with a STOP condition.

See Table 3 for the list of the internal registers and a description of each one.

If a read is requested by the master after a POR without first setting the command byte through a write, the device will NACK until a command byte-register address is set as described above.

Figure 31 shows an example of reading a single byte from a slave register.

Figure 31. Read from Register

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data. See Figure 32.

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This figure assumes the command byte has previously been programmed with 00h.

Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see the Reads section for these details).

Figure 32. Read Input Port Register