6.1 Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
|
MIN |
MAX |
UNIT |
VCC |
Supply voltage |
–0.5 |
6 |
V |
VI |
Input voltage (2) |
–0.5 |
6 |
V |
VO |
Output voltage(2) |
–0.5 |
6 |
V |
IIK |
Input clamp current |
VI < 0 |
|
–20 |
mA |
IOK |
Output clamp current |
VO < 0 |
|
–20 |
mA |
IIOK |
Input-output clamp current |
VO < 0 or VO > VCC |
|
±20 |
mA |
IOL |
Continuous output low current through a single P-port |
VO = 0 to VCC |
|
50 |
mA |
IOH |
Continuous output high current through a single P-port |
VO = 0 to VCC |
|
–50 |
mA |
ICC |
Continuous current through GND by all P-ports, INT, and SDA |
|
250 |
mA |
Continuous current through VCC by all P-ports |
|
–160 |
Tstg |
Storage temperature |
–65 |
150 |
°C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
|
VALUE |
UNIT |
V(ESD) |
Electrostatic discharge |
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) |
2000 |
V |
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) |
1000 |
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.
6.3 Recommended Operating Conditions
|
MIN |
MAX |
UNIT |
VCC |
Supply voltage |
1.65 |
5.5 |
V |
VIH |
High-level input voltage |
SCL, SDA |
VCC = 1.65 V to 5.5 V |
0.7 × VCC |
VCC(1) |
V |
A0, A1, RESET, P7–P0 |
VCC = 1.65 V to 2.7 V |
0.7 × VCC |
5.5 |
VCC = 3 V to 5.5 V |
0.8 × VCC |
5.5 |
VIL |
Low-level input voltage |
SCL, SDA |
VCC = 1.65 V to 5.5 V |
–0.5 |
0.3 × VCC |
V |
A0, A1, RESET, P7–P0 |
VCC = 1.65 V to 2.7 V |
–0.5 |
0.3 × VCC |
VCC = 3 V to 5.5 V |
–0.5 |
0.2 × VCC |
IOL |
Low-level output current |
Any P-port, P7–P0 |
|
25 |
mA |
IOH |
High-level output current |
Any P-port, P7–P0 |
|
–10 |
mA |
ICC |
Continuous current through GND |
All P-ports P7-P0, INT, and SDA |
|
200 |
mA |
Continuous current through VCC |
All P-ports P7-P0 |
|
–80 |
TA |
Operating free-air temperature |
–40 |
85 |
°C |
(1) The SCL and SDA pins shall not be at a higher potential than the supply voltage VCC in the application, or an increase in supply current, ICC, will result.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER |
TEST CONDITIONS |
VCC |
MIN |
TYP(1) |
MAX |
UNIT |
VIK |
Input diode clamp voltage |
II = –18 mA |
1.65 V to 5.5 V |
–1.2 |
|
|
V |
VPORR |
Power-on reset voltage, VCC rising |
VI = VCC or GND, IO = 0 |
|
|
1.2 |
1.5 |
V |
VPORF |
Power-on reset voltage, VCC falling |
VI = VCC or GND, IO = 0 |
|
0.75 |
1 |
|
V |
VOH |
P-port high-level output voltage(4) |
IOH = –8 mA |
1.65 V |
1.2 |
|
|
V |
2.3 V |
1.8 |
|
|
3 V |
2.6 |
|
|
4.5 V |
4.1 |
|
|
IOH = –10 mA |
1.65 V |
1.1 |
|
|
2.3 V |
1.7 |
|
|
3 V |
2.5 |
|
|
4.5 V |
4 |
|
|
IOL |
SDA (2) |
VOL = 0.4 V |
1.65 V to 5.5 V |
3 |
11 |
|
mA |
P port(5) |
VOL = 0.5 V |
1.65 V |
8 |
10 |
|
2.3 V |
8 |
13 |
|
3 V |
8 |
15 |
|
4.5 V |
8 |
17 |
|
VOL = 0.7 V |
1.65 V |
10 |
14 |
|
2.3 V |
10 |
17 |
|
3 V |
10 |
20 |
|
4.5 V |
10 |
24 |
|
INT (3) |
VOL = 0.4 V |
1.65 V to 5.5 V |
3 |
7 |
|
II |
SCL, SDA |
VI = VCC or GND |
1.65 V to 5.5 V |
|
|
±1 |
μA |
A0, A1, RESET |
|
|
±1 |
IIH |
P port |
VI = VCC |
1.65 V to 5.5 V |
|
|
1 |
μA |
IIL |
P port |
VI = GND |
1.65 V to 5.5 V |
|
|
–1 |
μA |
ICC |
Operating mode |
VI = VCC or GND, IO = 0, I/O = inputs, fscl = 400 kHz, No load tr = 3 ns |
5.5 V |
|
18 |
30 |
μA |
VI = VCC or GND, IO = 0, I/O = inputs, fscl = 400 kHz, No load tr,max = 300 ns |
5.5 V |
|
34 |
|
3.6 V |
|
15 |
|
2.7 V |
|
9 |
|
1.65 V |
|
5 |
|
VI = VCC or GND, IO = 0, I/O = inputs, fscl = 100 kHz, No load tr,max = 1 µs |
5.5 V |
|
20 |
|
3.6 V |
|
8 |
|
2.7 V |
|
5 |
|
1.65 V |
|
3 |
|
Standby mode |
VI = VCC or GND, IO = 0, I/O = inputs, fscl = 0 kHz, No load |
5.5 V |
|
1.9 |
3.5 |
μA |
3.6 V |
|
1.1 |
1.8 |
2.7 V |
|
1 |
1.6 |
1.65 V |
|
0.4 |
1 |
ΔICC |
Additional current in standby mode |
One P-port input at VCC – 0.6 V, Other P-port inputs at VCC or GND |
1.65 V to 5.5 V |
|
|
70 |
µA |
Ci |
SCL |
VI = VCC or GND |
1.65 V to 5.5 V |
|
4 |
5 |
pF |
Cio |
SDA |
VIO = VCC or GND |
1.65 V to 5.5 V |
|
5.5 |
6.5 |
pF |
P port |
|
8 |
9.5 |
(1) All typical values are at nominal supply voltage (1.8-, 2.5-, 3.3-, or 5-V VCC) and TA = 25°C.
(2) The SDA pin must be externally limited to a maximum of 12 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.
(3) The INT pin must be externally limited to a maximum of 7 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.
(4) Each P-port I/O configured as a high output must be externally limited to a maximum of 10 mA, and the total current sourced by all I/Os (P-ports P7-P0) through VCC must be limited to a maximum current of 80 mA.
(5) Each P-port I/O configured as a low output must be externally limited to a maximum of 25 mA, and the total current sunk by all I/Os (P-ports P7-P0, INT, and SDA) through GND must be limited to a maximum current of 200 mA.