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ZHCSDC5B April 2014 – November 2019 TCA9546A

PRODUCTION DATA.

封装选项

机械数据 (封装 | 引脚)

PW|16
- MPDS361A
D|16
- MPDS178G

散热焊盘机械数据 (封装 | 引脚)

订购信息

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, TCA9546A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

A power-on reset is shown in Figure 19.

Figure 19. V_CC is Lowered Below the POR Threshold, Then Ramped Back Up to V_CC

Table 2 specifies the performance of the power-on reset feature for TCA9546A for both types of power-on reset.

Table 2. Recommended Supply Sequencing And Ramp Rates⁽¹⁾

PARAMETER			MIN	MAX	UNIT
V_{CC_FT}	Fall time	See Figure 19	1	100	ms
V_{CC_RT}	Rise time	See Figure 19	0.1	100	ms
V_{CC_TRR}	Time to re-ramp (when V_CC drops below V_PORF(min) – 50 mV or when V_CC drops to GND)	See Figure 19	40		μs
V_{CC_GH}	Level that V_CC can glitch down to, but not cause a functional disruption when V_{CC_GW} = 1 μs	See Figure 20		1.2	V
V_{CC_GW}	Glitch width that will not cause a functional disruption when V_{CC_GH} = 0.5 × V_CC	See Figure 20		10	μs
V_PORF	Voltage trip point of POR on falling V_CC	See Figure 21	0.8	1.25	V
V_PORR	Voltage trip point of POR on rising V_CC	See Figure 21	1.05	1.5	V

(1) All supply sequencing and ramp rate values are measured at T_A = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 20 and Table 2 provide more information on how to measure these specifications.

Figure 20. Glitch Width and Glitch Height

V_POR is critical to the power-on reset. V_POR is the voltage level at which the reset condition is released and all the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs based on the V_CC being lowered to or from 0. Figure 21 and Table 2 provide more details on this specification.

Figure 21. V_POR