ZHCSJQ8C may   2019  – june 2023 TCA9548A-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Reset Timing Requirements
    8. 6.8 Switching Characteristics
    9. 6.9 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
      1. 8.4.1 RESET Input
      2. 8.4.2 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
      2. 8.5.2 Device Address
      3. 8.5.3 Bus Transactions
        1. 8.5.3.1 Writes
        2. 8.5.3.2 Reads
      4. 8.5.4 Control Register
      5. 8.5.5 RESET Input
      6. 8.5.6 Power-On Reset
  10.   Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  11.   Power Supply Recommendations
    1. 9.1 Power-On Reset Requirements
  12. 9 Layout
    1. 9.1 Layout Guidelines
    2. 9.2 Layout Example
  13. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 接收文档更新通知
    3. 10.3 支持资源
    4. 10.4 商标
    5. 10.5 静电放电警告
    6. 10.6 术语表
  14.   Mechanical, Packaging, and Orderable Information

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6.6 I2C Interface Timing Requirements

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 7-1)
MINMAXUNIT
STANDARD MODE
fsclI2C clock frequency0100kHz
tschI2C clock high time4μs
tsclI2C clock low time4.7μs
tspI2C spike time50ns
tsdsI2C serial-data setup time250ns
tsdhI2C serial-data hold time0(1)μs
ticrI2C input rise time1000ns
ticfI2C input fall time300ns
tocfI2C output (SDn) fall time (10 pF to 400 pF bus)300ns
tbufI2C bus free time between stop and start4.7μs
tstsI2C start or repeated start condition setup4.7μs
tsthI2C start or repeated start condition hold4μs
tspsI2C stop condition setup4μs
tvdL(Data)Valid-data time (high to low)(2)SCL low to SDA output low valid1μs
tvdH(Data)Valid-data time (low to high)(2)SCL low to SDA output high valid0.6μs
tvd(ack)Valid-data time of ACK conditionACK signal from SCL low
to SDA output low		1μs
CbI2C bus capacitive load400pF
FAST MODE
fsclI2C clock frequency0400kHz
tschI2C clock high time0.6μs
tsclI2C clock low time1.3μs
tspI2C spike time50ns
tsdsI2C serial-data setup time100ns
tsdhI2C serial-data hold time0(1)μs
ticrI2C input rise time20300ns
ticfI2C input fall time20 × (VCC / 5.5 V)300ns
tocfI2C output (SDn) fall time (10 pF to 400 pF bus)20 × (VCC / 5.5 V)300ns
tbufI2C bus free time between stop and start1.3μs
tstsI2C start or repeated start condition setup0.6μs
tsthI2C start or repeated start condition hold0.6μs
tspsI2C stop condition setup0.6μs
tvdL(Data)Valid-data time (high to low)(2)SCL low to SDA output low valid1μs
tvdH(Data)Valid-data time (low to high)(2)SCL low to SDA output high valid0.6μs
tvd(ack)Valid-data time of ACK conditionACK signal from SCL low
to SDA output low		1μs
CbI2C bus capacitive load400pF
(1) A device internally must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH min of the SCL signal), to bridge the undefined region of the falling edge of SCL.
(2) Data taken using a 1 kΩ pull-up resistor and 50 pF load (see Figure 7-2)
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