9.2.1 Design Requirements

A typical application of the TCA9548A contains one or more data pull-up voltages, V_DPUX, one for the master device (V_DPUM) and one for each of the selectable slave channels (V_DPU0 – V_DPU7). In the event where the master device and all slave devices operate at the same voltage, then V_DPUM = V_DPUX = VCC. In an application where voltage translation is necessary, additional design requirements must be considered to determine an appropriate V_CC voltage.

The A0, A1, and A2 pins are hardware selectable to control the slave address of the TCA9548A. These pins may be tied directly to GND or V_CC in the application.

If multiple slave channels are activated simultaneously in the application, then the total I_OL from SCL/SDA to GND on the master side is the sum of the currents through all pull-up resistors, R_p.

The pass-gate transistors of the TCA9548A are constructed such that the V_CC voltage can be used to limit the maximum voltage that is passed from one I²C bus to another.

Figure 14 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the Electrical Characteristics table). In order for the TCA9548A to act as a voltage translator, the V_pass voltage must be equal to or lower than the lowest bus voltage. For example, if the main bus is running at 5 V and the downstream buses are 3.3 V and 2.7 V, V_pass must be equal to or below 2.7 V to effectively clamp the downstream bus voltages. As shown in Figure 14, V_pass(max) is 2.7 V when the TCA9548A supply voltage is 4 V or lower, so the TCA9548A supply voltage could be set to 3.3 V. Pull-up resistors then can be used to bring the bus voltages to their appropriate levels (see Figure 13).