8.3.1 I/O Port

When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up (100 kΩ typical) to V_CC. The input voltage may be raised above V_CC to a maximum of 5.5 V, however it must be noted that because of the integrated 100 kΩ pull-up resistor it may result in current flow from I/O to VCC pin (Figure 15).

If the I/O is configured as an output, Q1 or Q2 is enabled depending on the state of the output port register. In this case, there are low impedance paths between the I/O pin and either V_CC or GND. The external voltage applied to this I/O pin must not exceed the recommended levels for proper operation.