8.6.3.1.2 Reads

The bus master first must send the TCA9554 address with the LSB set to a logic 0 (see Figure 19 for device address). The command byte is sent after the address and determines which register is accessed. After a restart, the device address is sent again but, this time, the LSB is set to a logic 1. Data from the register defined by the command byte then is sent by the TCA9554 (see Figure 25). The command byte does not increment automatically. If multiple bytes are read, data from the specified command byte/register is going to be continuously read.

See the Register Descriptions section for the list of the TCA9554's internal registers and a description of each one.

Figure 24 shows an example of reading a single byte from a slave register.

Figure 24. Read from Register

After a restart, the value of the register defined by the command byte matches the register being accessed when the restart occurred. Data is clocked into the register on the rising edge of the ACK clock pulse. After the first byte, additional bytes may be read, but the same register specified by the command byte is read.

Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number of data bytes received in one read transmission, but when the final byte is received, the bus master must not acknowledge the data.

A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read Input Port register).

B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address call and actual data transfer from the P port (see Figure 24 for these details).

Figure 25. Read Input Port Register