ZHCSDP5E December   2010  – February 2017 TCA9554A

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用范围
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 I/O Port
      2. 8.3.2 Interrupt Output (INT)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-On Reset
    5. 8.5 Programming
      1. 8.5.1 I2C Interface
    6. 8.6 Register Maps
      1. 8.6.1 Device Address
      2. 8.6.2 Control Register and Command Byte
      3. 8.6.3 Register Descriptions
        1. 8.6.3.1 Bus Transactions
          1. 8.6.3.1.1 Writes
          2. 8.6.3.1.2 Reads
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
        1. 9.2.1.1 Calculating Junction Temperature and Power Dissipation
        2. 9.2.1.2 Minimizing ICC When I/Os Control LEDs
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On Reset Requirements
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 文档支持
      1. 12.1.1 相关文档　
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

封装选项

机械数据 (封装 | 引脚)
散热焊盘机械数据 (封装 | 引脚)
订购信息

10 Power Supply Recommendations

10.1 Power-On Reset Requirements

In the event of a glitch or data corruption, the TCA9554A can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The power-on reset is shown in Figure 31.

TCA9554A pwron02_cps204.gif Figure 31. VCC is Lowered Below the POR Threshold, then Ramped Back Up to VCC

Table 8 specifies the performance of the power-on reset feature for the TCA9554A.

Table 8. Recommended Supply Sequencing and Ramp Rates(1)

PARAMETER MIN MAX UNIT
VCC_FT Fall rate See Figure 31 1 2000 ms
VCC_RT Rise rate See Figure 31 0.1 2000 ms
VCC_TRR Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) See Figure 31 2 μs
VCC_GH Level that VCCP can glitch down to, but not cause a functional disruption when VCC_GW = 1 μs See Figure 32 1.2 V
VCC_MV The minimum voltage that VCC can glitch down to without causing a reset (VCC_GH must not be violated) See Figure 32 1.5 V
VCC_GW Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC See Figure 32 10 μs
(1) All supply sequencing and ramp rate values are measured at TA = 25°C

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 32 and Table 8 provide more information on how to measure these specifications.

TCA9554A pwron03_scps254.gif Figure 32. Glitch Width and Glitch Height

VPORR is critical to the power-on reset. VPORR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of power-on-reset voltage differs based on the VCC being lowered to or from 0 (VPORR or VPORF). Figure 33 and Table 8 provide more details on this specification.

TCA9554A POR_waveform.gif Figure 33. Waveform Describing VCC Voltage Level at Which Power-On-Reset Occurs
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