ZHCSP01 July 2022 TCAL9539
ADVANCE INFORMATION
- 1 特性
- 2 应用
- 3 说明
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Device and Documentation Support
- 11Mechanical, Packaging, and Orderable Information
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- RTW|24
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9.3.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCAL9539 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in Figure 9-6 and Figure 9-7.
Figure 9-6 V is lowered below 0.2 V or 0 V and then ramped up
Figure 9-7 V is lowered below the POR threshold, then ramped back upTable 9-2 specifies the performance of the power-on reset feature for TCAL9539 for both types of power-on reset.
| PARAMETER(1)(2) | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|
| tFT | Fall rate | See Figure 9-6 | 0.1 | 2000 | ms | |
| tRT | Rise rate | See Figure 9-6 | 0.1 | 2000 | ms | |
| tTRR_GND | Time to re-ramp (when VCC drops to GND) | See Figure 9-6 | 1 | μs | ||
| tTRR_POR50 | Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV) | See Figure 9-7 | 1 | μs | ||
| VCC_GH | Level that V can glitch down to, but not cause a functional disruption when V = 1 μs | See Figure 9-8 | 1.0 | V | ||
| tGW | Glitch width that will not cause a functional disruption when V = 0.5 × VCCx | See Figure 9-8 | 10 | μs | ||
| VPORF | Voltage trip point of POR on falling VCC | 0.6 | V | |||
| VPORR | Voltage trip point of POR on rising VCC | 1.0 | V | |||
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 9-8 and Table 9-2 provide more information on how to measure these specifications.
Figure 9-8 Glitch
Width and Glitch HeightVPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the V being lowered to or from 0. Figure 9-9 and Table 9-2 provide more details on this specification.
Figure 9-9 VPOR