| Thermal Metric(1) | TEST CONDITIONS | TCAN1042 | UNIT |
|---|
| D (SOIC) | DRB (VSON) |
|---|
| 8 Pins | 8 Pins |
|---|
| RθJA | Junction-to-air thermal resistance | High-K thermal resistance(2) | 105.8 | 48.3 | °C/W |
| RθJB | Junction-to-board thermal resistance(3) | | 46.8 | 17.2 | °C/W |
| RθJC(TOP) | Junction-to-case (top) thermal resistance(4) | | 48.3 | 37.6 | °C/W |
| ΨJT | Junction-to-top characterization parameter(5) | | 8.7 | 1.8 | °C/W |
| ΨJB | Junction-to-board characterization parameter(6) | | 46.2 | 17.1 | °C/W |
| TTSD | Thermal shutdown temperature | | 170 | 170 | °C |
| TTSD_HYS | Thermal shutdown hysteresis | | 5 | 5 | °C |
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, High-K board, as specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.
(4) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(5) The junction-to-top characterization parameter, ΨJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ΨJB estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).