The CAN bus has two logical states during operation: recessive and dominant. See Figure 8-2 and Figure 8-3.

In the recessive bus state the bus is biased to a common mode of approximately V_CC/2 (2.5 V) via the high resistance internal input resistors of the receiver of each node on the bus. Recessive is equivalent to a logic high and is typically a differential voltage on the bus of approximately 0 V.

The dominant bus state is when the bus is driven differentially by one or more drivers. Current flows through the termination resistors and generates a differential voltage on the bus. Dominant is equivalent to a logic low and is a differential voltage on the bus greater than the minimum threshold for a CAN dominant. A dominant state overwrites the recessive state.

During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential voltage of the bus is greater than the differential voltage of a single driver.

The host microprocessor of the CAN node uses the TXD terminal to drive the bus and receives data from the bus on the RXD terminal.

The TCAN1043xx-Q1 transceivers has a third bus state in low power standby mode where the bus terminals are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 8-2 and Figure 8-3.

Figure 8-2 Bus States (Physical Bit Representation)

A. Normal and Silent Modes

B. Sleep and Standby Modes

Figure 8-3 Bias Unit (Recessive Common Mode Bias) and Receiver

*The enable pin can be in a logical high or low state while in sleep mode but since it has an internal pull-down, the lowest possible power consumption occurs when the pin is left either floating or pulled low externally.

Figure 8-4 State Diagram