While the CAN driver is in active mode a TXD dominant state timeout circuit prevents the local node from blocking network communication in event of a hardware or software failure where TXD is held dominant longer than the timeout period, t > t_TXDDTO. The TXD dominant state timeout circuit is triggered by a falling edge on the TXD pin. If no rising edge is seen before on TXD before t > t_TXDDTO than the CAN driver is disabled releasing the bus lines to the recessive level. This keeps the bus free for communication between other nodes on the network.

The CAN driver will be activated again on the next dominant-to-recessive transition on the TXD pin. During a TXDDTO fault the high-speed receiver remains active and the RXD output pin will mirror the CAN bus.

Figure 8-3 Timing Diagram for TXD DTO

The minimum dominant TXD time allowed by the dominant state timeout circuit limits the minimum possible transmitted data rate of the transceiver. The CAN protocol allows a maximum of eleven successive dominant bits to be transmitted in the worst case, where five successive dominant bits are followed immediately by an error frame. The minimum transmitted data rate may be calculated using the minimum t_TXDDTO time in Equation 1.