The CAN bus has two logical states during operation: recessive and dominant. See Figure 8-2 and Figure 8-3.

A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to V_CC/2 via the high-resistance internal input resistors (R_IN) of the receiver and corresponds to a logic high on the TXD and RXD pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver.

The TCAN1044A(V)-Q1 transceiver implements a low-power standby (STB) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 8-2 and Figure 8-3.

Figure 8-2 Bus States

A. A - Normal Mode B - Standby Mode

Figure 8-3 Simplified Recessive Common Mode Bias Unit and Receiver