8.3.2 CAN Bus States

The CAN bus has two logical states during operation: recessive and dominant. See Figure 12 and Figure 13.

A dominant bus state occurs when the bus is driven differentially and corresponds to a logic low on the TXD and RXD pins. A recessive bus state occurs when the bus is biased to V_CC/2 via the high-resistance internal input resistors (R_IN) of the receiver and corresponds to a logic high on the TXD and RXD pins.

A dominant state overwrites the recessive state during arbitration. Multiple CAN nodes may be transmitting a dominant bit at the same time during arbitration, and in this case the differential voltage of the bus is greater than the differential voltage of a single driver.

The TCAN1044V transceiver implements a low-power standby (STB) mode which enables a third bus state where the bus pins are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 12 and Figure 13.

Figure 12. Bus States

A. Normal Mode

B. Standby Mode

Figure 13. Simplified Recessive Common Mode Bias Unit and Receiver