ZHCSIR6C September 2018 – February 2022 TCAN1046V-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Device Switching Characteristics | ||||||
| tPROP(LOOP1) | Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant | Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF VIO = 2.8 V to 5.5 V See Figure 7-4 |
125 | 210 | ns | |
| tPROP(LOOP1) | Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant | Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF VIO = 1.7 V See Figure 7-4 |
165 | 255 | ns | |
| tPROP(LOOP2) | Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive | Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF VIO = 2.8 V to 5.5 V See Figure 7-4 |
150 | 210 | ns | |
| tPROP(LOOP2) | Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive | Normal mode, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF VIO = 1.7 V See Figure 7-4 |
180 | 255 | ns | |
| tMODE | Mode change time, from normal to standby or from standby to normal | See Figure 7-5 |
20 | µs | ||
| tWK_FILTER | Filter time for a valid wake-up pattern | See Figure 8-5 | 0.5 | 1.8 | µs | |
| tWK_TIMEOUT | Bus wake-up timeout | See Figure 8-5 | 0.8 | 6 | ms | |
| Driver Switching Characteristics | ||||||
| tpHR | Propagation delay time, high TXD to driver recessive (dominant to recessive) | STB = 0 V, RL = 60 Ω, CL = 100 pF See Figure 7-2 and Figure 7-6 |
80 | ns | ||
| tpLD | Propagation delay time, low TXD to driver dominant (recessive to dominant) | 70 | ns | |||
| tsk(p) | Pulse skew (|tpHR - tpLD|) | 20 | ns | |||
| tR | Differential output signal rise time | 30 | ns | |||
| tF | Differential output signal fall time | 50 | ns | |||
| tTXD_DTO | Dominant timeout | 1.2 | 4.0 | ms | ||
| Receiver Switching Characteristics | ||||||
| tpRH | Propagation delay time, bus recessive input to high output (dominant to recessive) | STB = 0 V, CL(RXD) = 15 pF See Figure 7-3 |
90 | ns | ||
| tpDL | Propagation delay time, bus dominant input to low output (recessive to dominant) | 65 | ns | |||
| tR | RXD output signal rise time | 10 | ns | |||
| tF | RXD output signal fall time | 10 | ns | |||
| FD Timing Characteristics | ||||||
| tBIT(BUS) | Bit time on CAN bus output pins tBIT(TXD) = 500 ns |
STB = 0 V, RL = 60 Ω, CL = 100 pF,
CL(RXD) = 15 pF ΔtREC = tBIT(RXD) - tBIT(BUS) See Figure 7-4 |
450 | 530 | ns | |
| tBIT(BUS) | Bit time on CAN bus output pins tBIT(TXD) = 200 ns |
155 | 210 | ns | ||
| tBIT(RXD) | Bit time on RXD output pins tBIT(TXD) = 500 ns |
400 | 550 | ns | ||
| tBIT(RXD) | Bit time on RXD output pins tBIT(TXD) = 200 ns |
120 | 220 | ns | ||
| tREC | Receiver timing symmetry tBIT(TXD) = 500 ns |
-50 | 20 | ns | ||
| tREC | Receiver timing symmetry tBIT(TXD) = 200 ns |
-45 | 15 | ns | ||