ZHCSO46 December 2021 TCAN1057AEV-Q1
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| Device Switching Characteristics | ||||||
| tPROP(LOOP1) | Total loop delay Driver input (TXD) to receiver output (RXD), recessive to dominant |
S = 0 V, VIO = 2.8 V to 5.5 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; See Figure 7-4 |
125 | 210 | ns | |
| tPROP(LOOP1) | Total loop delay Driver input (TXD) to receiver output (RXD), recessive to dominant |
S = 0 V, VIO = 1.7 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; See Figure 7-4 |
165 | 255 | ns | |
| tPROP(LOOP2) | Total loop delay Driver input (TXD) to receiver output (RXD), dominant to recessive |
S = 0 V, VIO = 2.8 V to 5.5 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; See Figure 7-4 |
150 | 210 | ns | |
| tPROP(LOOP2) | Total loop delay Driver input (TXD) to receiver output (RXD), dominant to recessive |
S = 0 V, VIO = 1.7 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF; See Figure 7-4 |
180 | 255 | ns | |
| tMODE | Mode change time, from normal to silent or from silent to normal | See Figure 7-5 | 20 | µs | ||
| Driver Switching Characteristics | ||||||
| tpHR | Propagation delay time, high TXD to driver recessive (dominant to recessive) | S = 0 V RL = 60 Ω, CL = 100 pF; See Figure 7-2 |
80 | ns | ||
| tpLD | Propagation delay time, low TXD to driver dominant (recessive to dominant) | 70 | ns | |||
| tsk(p) | Pulse skew (|tpHR - tpLD|) | 14 | ns | |||
| tR | Differential output signal rise time | 25 | ns | |||
| tF | Differential output signal fall time | 50 | ns | |||
| tTXD_DTO | Dominant timeout | S = 0 V RL = 60 Ω, CL = 100 pF; See Figure 7-6 |
1.2 | 4.0 | ms | |
| Receiver Switching Characteristics | ||||||
| tpRH | Propagation delay time, bus recessive input to high output (dominant to recessive) | S = 0 V CL(RXD) = 15 pF; See Figure 7-3 |
81 | ns | ||
| tpDL | Propagation delay time, bus dominant input to low output (recessive to dominant) | 66 | ns | |||
| tR | RXD output signal rise time | 10 | ns | |||
| tF | RXD output signal fall time | 10 | ns | |||
| FD Timing Characteristics | ||||||
| tBIT(BUS) | Bit time on CAN bus output pins tBIT(TXD) = 500 ns |
S = 0 V RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF ΔtREC = tBIT(RXD) - tBIT(BUS) ; See Figure 7-4 |
450 | 525 | ns | |
| Bit time on CAN bus output pins tBIT(TXD) = 200 ns |
160 | 205 | ns | |||
| Bit time on CAN bus output pins tBIT(TXD) = 125 ns(1) |
85 | 130 | ns | |||
| tBIT(RXD) | Bit time on RXD output pins tBIT(TXD) = 500 ns |
410 | 540 | ns | ||
| Bit time on RXD output pins tBIT(TXD) = 200 ns |
130 | 210 | ns | |||
| Bit time on RXD output pins tBIT(TXD) = 125 ns(1) |
75 | 135 | ns | |||
| ΔtREC | Receiver timing symmetry tBIT(TXD) = 500 ns |
-50 | 20 | ns | ||
| Receiver timing symmetry tBIT(TXD) = 200 ns |
-40 | 10 | ns | |||
| Receiver timing symmetry tBIT(TXD) = 125 ns(1) |
-40 | 10 | ns | |||