ZHCSPG0 December 2021 TCAN1167-Q1
PRODUCTION DATA
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
Supply Switching Characteristics | ||||||||
tPOWER_UP | CAN supply power up time | CVCCOUT = 10 µF See Figure 8-9 |
1.8 | 4 | ms | |||
tUV(SUP) | VSUP filter time (rising and falling) | 4 | 25 | µs | ||||
tUV(VCCOUT) | VCCOUT filter time (rising and falling) | Time for device to enter sleep state reset state once UVCCOUT is reached | 30 | µs | ||||
Device Switching Characteristics | ||||||||
tUV(nRST) | Undervoltage detection delay time nRST low | 10 | 50 | µs | ||||
tWK_FILTER | Bus time to meet filtered bus requirments for wakeup request | See Figure 9-15 |
0.5 | 1.8 | µs | |||
tWK_TIMEOUT | Bus wakeup timeout value | 0.8 | 2 | ms | ||||
tSILENCE | Time out for bus inactivity | 0.9 | 1.2 | s | ||||
tINACTIVE | Hardware timer for failsafe and power up inactivity(1) | 3 | 4 | 5 | min | |||
tBIAS | Time from the start of a dominant-recessive-dominant sequence until Vsym ≥ 0.1 | Each phase: 6 μs See Figure 8-11 |
250 | µs | ||||
tCAN(ACTIVE) | Time from switching to CAN active mode to transceiver ready to transmit | VCCOUT > UVVCCOUT(R) | 25 | us | ||||
tPROP(LOOP1) | Total loop delay, driver input (TXD) to receiver output (RXD) Recessive to dominant |
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 8-6 |
100 | 160 | ns | |||
tPROP(LOOP2) | Total loop delay, driver input (TXD) to receiver output (RXD) Dominant to recessive |
RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF See Figure 8-6 |
120 | 175 | ns | |||
tmode_slp_reset | WUP or LWU event to INH asserted high, see | 50 | µs | |||||
Driver Switching Characteristics | ||||||||
tpHR | Propagation delay time, high TXD to driver recessive | RL = 60 Ω, CL = 100 pF, RCM = open See Figure 8-2 |
20 | 35 | 70 | ns | ||
tpLD | Propagation delay time, low TXD to driver dominant | 15 | 40 | 70 | ns | |||
tsk(p) | Pulse skew (|tpHR - tpLD|) | 10 | 20 | ns | ||||
tR | Differential output signal rise time | 40 | ns | |||||
tF | Differential output signal fall time | 45 | ns | |||||
tTXD_DTO | Dominant timeout | RL = 60 Ω, CL = open See Figure 8-7, TXD = 0 V |
1.2 | 3.8 | ms | |||
Receiver Switching Characteristics | ||||||||
tpRH | Propagation delay time, bus recessive input to high RXD | CL(RXD) = 15 pF See Figure 8-3 |
25 | 80 | 140 | ns | ||
tpDL | Propagation delay time, bus dominant input to RXD low output | CL(RXD) = 15 pF See Figure 8-3 |
20 | 50 | 110 | ns | ||
tR | Output signal rise time (RXD) | CL(RXD) = 15 pF See Figure 8-3 |
8 | ns | ||||
tF | Output signal fall time (RXD) | CL(RXD) = 15 pF See Figure 8-3 |
5 | ns | ||||
WAKE Characteristics | ||||||||
tWAKE | Time required for INH pin to go high after an local wake event occurs on the WAKE pin | 40 | µs | |||||
nRST Characteristics | ||||||||
tnRST | Minimum low time for reset | Input pulse width | 15 | µs | ||||
tnRST(cold) | Output pulse width | Cold crank | 20 | 27 | ms | |||
tnRST(warm) | Output pulse width | Warm crank | 1 | 1.5 | ms | |||
SPI Switching Characteristics | ||||||||
fSCK | SCK, SPI clock frequency | Normal, standby, and silent modes | 4 | MHz | ||||
tSCK | SCK, SPI clock period | Normal, standby, and silent modes; See Figure 8-13 | 250 | ns | ||||
tRSCK | SCK rise time | See Figure 8-12 | 40 | ns | ||||
tFSCK | SCK fall time | See Figure 8-12 | 40 | ns | ||||
tSCKH | SCK, SPI clock high | Normal, standby, and silent modes; See Figure 8-13 | 125 | ns | ||||
tSCKL | SCK, SPI clock low | Normal, standby, and silent modes; See Figure 8-13 | 125 | ns | ||||
tACC | First read access time from chip select | 50 | ns | |||||
tCSS | Chip select setup time | See Figure 8-12 | 100 | ns | ||||
tCSH | Chip select hold time | See Figure 8-12 | 100 | ns | ||||
tCSD | Chip select disable time | See Figure 8-12 | 50 | ns | ||||
tSISU | Data in setup time | Normal, standby, and silent modes; See Figure 8-12 | 50 | ns | ||||
tSIH | Data in hold time | Normal, standby, and silent modes; See Figure 8-12 | 50 | ns | ||||
tSOV | Data out valid | Normal, standby, and silent modes; See Figure 8-13 | 80 | ns | ||||
tRSO | SO rise time | See Figure 8-13 | 40 | ns | ||||
tFSO | SO fall time | See Figure 8-13 | 40 | ns | ||||
CAN FD Timing Characteristics | ||||||||
tBIT(BUS) | Bit time on CAN bus output pins with tBIT(TXD) = 500 ns | RL = 60 Ω, CL = 100 pF CL(RXD) = 15 pF ΔtREC = tBIT(RXD) - tBIT(BUS) See Figure 8-6 |
435 | 530 | ns | |||
Bit time on CAN bus output pins with tBIT(TXD) = 200 ns | 155 | 210 | ns | |||||
Bit time on CAN bus output pins with tBIT(TXD) = 125 ns | 80 | 140 | ns | |||||
tBIT(RXD) | Bit time on RXD output pins with tBIT(TXD) = 500 ns | RL = 60 Ω, CL = 100 pF CL(RXD) = 15 pF ΔtREC = tBIT(RXD) - tBIT(BUS) See Figure 8-6 |
400 | 550 | ns | |||
Bit time on RXD output pins with tBIT(TXD) = 200 ns | 120 | 220 | ns | |||||
Bit time on RXD output pins with tBIT(TXD) = 125 ns | 80 | 135 | ns | |||||
ΔtREC | Receiver timing symmetry with tBIT(TXD) = 500 ns | RL = 60 Ω, CL = 100 pF CL(RXD) = 15 pF ΔtREC = tBIT(RXD) - tBIT(BUS) See Figure 8-6 |
-50 | 20 | ns | |||
Receiver timing symmetry with tBIT(TXD) = 200 ns | -45 | 15 | ns | |||||
Receiver timing symetry with tBIT(TXD) = 125 ns | -40 | 10 | ns |