A Question and Answer (Q&A) watchdog is a type of watchdog where instead of simply resetting the watchdog via a SPI write, the MCU must read a ‘question’ from the TCAN1469-Q1, do math based on the question and then write the computed answers back to the TCAN1469-Q1. The correct answer is a 4-byte response. Each byte must be written in order and with the correct timing to have a correct answer.

There are 2 watchdog windows, referred to as WD Response window #1 and WD Response window #2 (Figure 8-31 WD QA Windows as example). The size of each window is 50% of the total watchdog window time, t_{WD_RESP_WIN1} + t_{WD_RESP_WIN2}, which is selected from the WD_TIMER and WD_PRE register bits.

Each watchdog question and answer is a full watchdog cycle. The general process is that the MCU reads the question during WD Response Window #1. The CPU must perform a mathematical function on the question, resulting in 4 bytes of answers. 3 of the 4 answer bytes must be written to the answer register within the WD Response Window #1, in correct order. The last answer must be written to the answer register after the first response window, inside of WD Response Window #2. If all 4 answer bytes were correct and in the correct order, then the response is considered good, the error counter is decremented and a new question is generated, starting the cycle over again. Once the fourth answer is written into WD Response Window #2, that window is terminated and a new WD Response Window #1 is started. The General Question & Answer timing diagram Figure 8-30 provides information on how the response windows may align. Response Window 1 is associated to Closed Window in the window WD timing diagram and Response Window 2 is associated to the Open Window with all the same rules and timing information.

Figure 8-30 General Question & Answer Timing Diagram.

If anything is incorrect or missed, the response is considered bad and the watchdog question will NOT change. In addition, an error counter is incremented. Once this error counter exceeds the threshold (defined in the WD_ERR_CNT_SET register field), the watchdog failure action is performed. Examples of actions are an interrupt, or reset toggle, and so no.

A. The MCU is not required to request the WD question. The MCU can start with correct answers, WD_ANSWER_RESP_x bytes anywhere within RESPONSE WINDOW 1. The new WD question is always generated within one system clock cycle after the final WD_ANSWER_RESP_0 answer during the previous WD Q&A sequence run.

B. The MCU can schedule other SPI commands between the WD_ANSWER_RESP_x responses (even a command requesting the WD question) without any impact to the WD function as long as the WD_ANSWER_RESP_[3:1] bytes are provided within the RESPONSE WINDOW 1 and WD_ANSWER_RESP_0 is provided within the RESPONSE WINDOW 2.

Figure 8-31 WD Q&A Sequence Run