Upon activation of the selective wake up function and upon the expiration of t_SILENCE the CAN frame error counter is set to zero. This error counter determines the CAN frame errors detected by the device. The error counter is at 8'h45 and is called FRAME_CNTx.

The initial counter value is zero and is incremented by 1 for every received frame error detected (stuff bit, CRC or CRC delimiter form error). The counter is decremented by 1 for every correctly received CAN frame assuming the counter is not zero. If the device is set for passive on CAN with flexible data rate frames, any frame detected as a CAN FD frame has no impact on the frame error counter (no increment or decrement). If a valid Classical CAN frame has been received and the counter is not zero the counter shall be decremented by one. Dominant bits between the CRC delimiter and the end of the intermission field do not increase the frame error counter.

On each increment or decrement of the error counter, the decoder unit waits for nBits_idle recessive bits before considering a dominant bit as a start of frame (SOF). See Figure 8-22 for the position of the mandatory start of frame detection when classic CAN frame was received and in case of error scenario.

Figure 8-22 Mandatory SOF Detection after Classic CAN Frames and Error Scenarios

The default value for the frame error counter threshold is 31, so that on the 32nd error, the frame overflow flag (FRAME_OVF) is set.

When the WUP is sent, the CAN bus will bias to a recessive level, activating the WUF receiver. Up to four (or eight when bit rate > 500kbps) consecutive Classic CAN data and/or remote frames that start after the bias reaction time, t_Bias, has elapsed might be either ignored, no error counter increase of failure, or judged as erroneous (error counter increases even in case of no error).

Received frames in CEFF with non-nominal reserved bits (SRR, r0) dp not lead to an increase of the error counter.

The frame error counter is compared to the frame error counter threshold, FRAME_CNT_THRESHOLD in 8'h46. If the counter overflows the threshold the frame error overflow flag, FRAME_OVF, is set. The default value for the frame error counter threshold is 31 so that on the 32nd error the overflow flag is set. However, if the application requires a different frame error count overflow threshold the required value may be programmed into the FRAME_CNT_THRESHOLD register.

The counter is reset by the following: disabling the frame detection, CANSLNT flag set, and setting register 8'h46 = 1b.

The description for the errors detected:

• Stuff bit error: A stuff bit error is detected when the 6th consecutive bit of the same state (level) is received. CAN message coding should have had a stuff bit at this bit position in the data stream.
• CRC error: The CRC sequence consists of the result of the CRC calculation by the transmitting node. This device calculates the CRC with the same polynomial as the transmitting node. A CRC error is detected if the calculated result is not the same as the result received in the CRC sequence.
• CRC delimiter error: The CRC delimiter error is detected when a bit of the wrong state (logic low / dominant) is received in the CRC delimiter bit position which is defined as logic high (recessive).