ZHCSPU9 February   2024 TCAN1465-Q1 , TCAN1469-Q1

ADVANCE INFORMATION  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  VCC Pin
      4. 8.3.4  GND
      5. 8.3.5  INH/LIMP Pin
      6. 8.3.6  WAKE Pin
      7. 8.3.7  TXD Pin
      8. 8.3.8  RXD Pin
      9. 8.3.9  SDO or nINT Interrupt Pin
      10. 8.3.10 nCS Pin
      11. 8.3.11 SCK
      12. 8.3.12 SDI
      13. 8.3.13 CANH and CANL Bus Pins
      14. 8.3.14 CAN FD SIC Transceiver
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Listen Only Mode
      4. 8.4.4 Sleep Mode
        1. 8.4.4.1 Bus Wake via RXD Request (BWRR) in Sleep Mode
        2. 8.4.4.2 Local Wake Up (LWU) via WAKE Input Terminal
      5. 8.4.5 Selective Wake-up
        1. 8.4.5.1 Selective Wake Mode
        2. 8.4.5.2 Frame Detection
        3. 8.4.5.3 Wake-Up Frame (WUF) Validation
        4. 8.4.5.4 WUF ID Validation
        5. 8.4.5.5 WUF DLC Validation
        6. 8.4.5.6 WUF Data Validation
        7. 8.4.5.7 Frame error counter
        8. 8.4.5.8 CAN FD Frame Tolerance
      6. 8.4.6 Fail-safe Features
        1. 8.4.6.1 Sleep Mode via Sleep Wake Error
        2. 8.4.6.2 Fail-safe Mode
      7. 8.4.7 Protection Features
        1. 8.4.7.1 Driver and Receiver Function
        2. 8.4.7.2 Floating Terminals
        3. 8.4.7.3 TXD Dominant Time Out (DTO)
        4. 8.4.7.4 CAN Bus Short Circuit Current Limiting
        5. 8.4.7.5 Thermal Shutdown
        6. 8.4.7.6 Under-Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.7.6.1 UVSUP, UVCC
          2. 8.4.7.6.2 UVIO
            1. 8.4.7.6.2.1 Fault Behavior
        7. 8.4.7.7 Watchdog (TCAN1469-Q1)
          1. 8.4.7.7.1 Watchdog Error Counter
          2. 8.4.7.7.2 Watchdog SPI Control Programming
            1. 8.4.7.7.2.1 Watchdog Configuration Registers Lock and Unlock
          3. 8.4.7.7.3 Watchdog Timing
          4. 8.4.7.7.4 Question and Answer Watchdog
            1. 8.4.7.7.4.1 WD Question and Answer Basic Information
            2. 8.4.7.7.4.2 Question and Answer Register and Settings
            3. 8.4.7.7.4.3 WD Question and Answer Value Generation
              1. 8.4.7.7.4.3.1 Answer Comparison
              2. 8.4.7.7.4.3.2 Sequence of the 2-bit Watchdog Answer Counter
            4. 8.4.7.7.4.4 Question and Answer WD Example
              1. 8.4.7.7.4.4.1 Example Configuration for Desired Behavior
              2. 8.4.7.7.4.4.2 Example of Performing a Question and Answer Sequence
      8. 8.4.8 Bus Fault Detection and Communication (TCAN1469-Q1)
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCK):
        3. 8.5.1.3 SPI Serial Data Input (SDI):
        4. 8.5.1.4 SPI Serial Data Output (SDO):
  10. 9 Application Information Disclaimer
    1. 9.1 Application Information
      1. 9.1.1 Signal Improvement Capable (SIC)
      2. 9.1.2 CAN Termination
        1. 9.1.2.1 Termination
        2. 9.1.2.2 CAN Bus Biasing
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Design Procedure
        1. 9.2.1.1 Brownout
      2. 9.2.2 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Registers
    1. 10.1 Register Maps
      1. 10.1.1  DEVICE_ID_y Register (Address = 0h + formula) [reset = value]
      2. 10.1.2  REV_ID_MAJOR Register (Address = 8h) [reset = 01h]
      3. 10.1.3  REV_ID_MINOR Register (Address = 9h) [reset = 00h]
      4. 10.1.4  SPI_RSVD_x Register (Address = Ah + formula) [reset = 00h]
      5. 10.1.5  Scratch_Pad_SPI Register (Address = Fh) [reset = 00h]
      6. 10.1.6  MODE_CNTRL Register (Address = 10h) [reset = 04h]
      7. 10.1.7  WAKE_PIN_CONFIG Register (Address = 11h) [reset = 4h]
      8. 10.1.8  PIN_CONFIG Register (Address = 12h) [reset = 00h]
      9. 10.1.9  WD_CONFIG_1 Register (Address = 13h) [reset = 15h]
      10. 10.1.10 WD_CONFIG_2 Register (Address = 14h) [reset = 02h]
      11. 10.1.11 WD_INPUT_TRIG Register (Address = 15h) [reset = 00h]
      12. 10.1.12 WD_RST_PULSE Register (Address = 16h) [reset = 07h]
      13. 10.1.13 FSM_CONFIG Register (Address = 17h) [reset = 00h]
      14. 10.1.14 FSM_CNTR Register (Address = 18h) [reset = 00h]
      15. 10.1.15 DEVICE_RST Register (Address = 19h) [reset = 00h]
      16. 10.1.16 DEVICE_CONFIG1 Register (Address = 1Ah) [reset = 00h]
      17. 10.1.17 DEVICE_CONFIG2 Register (Address = 1Bh) [reset = 0h]
      18. 10.1.18 SWE_EN Register (Address 1Ch) [reset = 04h]
      19. 10.1.19 SDO_CONFIG Register (Address = 29h) [reset = 00h]
      20. 10.1.20 WD_QA_CONFIG Register (Address = 2Dh) [reset = 00h]
      21. 10.1.21 WD_QA_ANSWER Register (Address = 2Eh) [reset = 00h]
      22. 10.1.22 WD_QA_QUESTION Register (Address = 2Fh) [reset = 3Ch]
      23. 10.1.23 SW_ID1 Register (Address = 30h) [reset = 00h]
      24. 10.1.24 SW_ID2 Register (Address = 31h) [reset = 00h]
      25. 10.1.25 SW_ID3 Register (Address = 32h) [reset = 00h]
      26. 10.1.26 SW_ID4 Register (Address = 33h) [reset = 00h]
      27. 10.1.27 SW_ID_MASK1 Register (Address = 34h) [reset = 00h]
      28. 10.1.28 SW_ID_MASK2 Register (Address = 35h) [reset = 00h]
      29. 10.1.29 SW_ID_MASK3 Register (Address = 36h) [reset = 00h]
      30. 10.1.30 SW_ID_MASK4 Register (Address = 37h) [reset = 00h]
      31. 10.1.31 SW_ID_MASK_DLC Register (Address = 38h) [reset = 00h]
      32. 10.1.32 DATA_y Register (Address = 39h + formula) [reset = 00h]
      33. 10.1.33 SW_RSVD_y Register (Address = 41h + formula) [reset = 00h]
      34. 10.1.34 SW_CONFIG_1 Register (Address = 44h) [reset = 50h]
      35. 10.1.35 SW_CONFIG_2 Register (Address = 45h) [reset = 00h]
      36. 10.1.36 SW_CONFIG_3 Register (Address = 46h) [reset = 1Fh]
      37. 10.1.37 SW_CONFIG_4 Register (Address = 47h) [reset = 00h]
      38. 10.1.38 SW_CONFIG_RSVD_y Register (Address = 48h + formula) [reset = 00h]
      39. 10.1.39 DEVICE_CONFIGx Register (Address = 4Bh) [reset = 0h]
      40. 10.1.40 INT_GLOBAL Register (Address = 50h) [reset = 00h]
      41. 10.1.41 INT_1 Register (Address = 51h) [reset = 00h]
      42. 10.1.42 INT_2 Register (Address = 52h) [reset = 40h]
      43. 10.1.43 INT_3 Register (Address 53h) [reset = 00h]
      44. 10.1.44 INT_CANBUS Register (Address = 54h) [reset = 00h]
      45. 10.1.45 INT_GLOBAL_ENABLE (Address = 55h) [reset = 00h]
      46. 10.1.46 INT_ENABLE_1 Register (Address = 56h) [reset = FFh]
      47. 10.1.47 INT_ENABLE_2 Register (Address = 57h) [reset = 1Fh]
      48. 10.1.48 INT_ENABLE_3 Register (Address = 58h) [reset = 0h]
      49. 10.1.49 INT_ENABLE_CANBUS Register (Address = 59h) [reset = 7Fh]
      50. 10.1.50 INT_RSVD_y Register (Address = 5Ah + formula) [reset = 00h]
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 CAN Transceiver Physical Layer Standards:
      2. 11.1.2 EMC Requirements:
      3. 11.1.3 Conformance Test Requirements:
      4. 11.1.4 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 Trademarks
    5. 11.5 静电放电警告
    6. 11.6 术语表
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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6.7 Electrical Characteristics

parameters valid across -40℃ ≤ TJ ≤ 150℃, 4.75V ≤ VCC ≤ 5.25V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CAN DRIVER ELECTRICAL CHARACTERISTICS
VO(D) Bus output voltage (dominant) CANH See Figure 9-4 VTXD = 0V, RL =45Ω to 65Ω, CL = open, RCM = open 3 4.26 V
Bus output voltage (dominant) CANL 0.75 2.01 V
VO(R) Bus output voltage (recessive) for CANH and CANL See Figure 9-1 and Figure 9-4 VTXD = VIO, RL = open (no load), RCM = open 2 2.5 3 V
V(DIFF) Differential voltage –42 42 V
VOD(R) Terminated bus output voltage (recessive) for CANH and CANL VTXD = VIO, 45Ω ≤ RL ≤ 65Ω, Split termination capacatance 4.7nF 2.256 2.756 V
VDIFF Terminated differential voltage rating VTXD = VIO, 45Ω ≤ RL ≤ 65Ω, Split termination capacatance 4.7nF –0.05 0.05 V
VOD(D) Differential output voltage (dominant); extended bus load See Figure 9-1 and Figure 9-4, VTXD = 0V, 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open 1.5 3 V
See Figure 9-1 and Figure 9-4, VTXD = 0V, 45Ω ≤ RL ≤ 70Ω, CL = open, RCM = open 1.5 3.3 V
See Figure 9-1 and Figure 9-4, VTXD = 0V, RL = 2.24kΩ, CL = open, RCM = open 1.5 5 V
VOD(R) Differential output voltage (recessive) See Figure 9-1 and Figure 9-4, VTXD = VIO, RL = 60Ω, CL = open, RCM = open –120 12 mV
See Figure 9-1 and Figure 9-4, VTXD = VIO, RL = open (no load), CL = open, RCM = open –50 50 mV
VO(INACT) Bus output voltage on CANH with bus biasing inactive (STBY) See Figure 9-1 and Figure 9-4, VTXD = VIO, RL = open, CL = open, RCM = open –0.1 0.1 V
Bus output voltage on CANL with bus biasing inactive (STBY) –0.1 0.1 V
Bus output voltage on CANH - CANL (recessive) with bus biasing inactive (STBY) –0.2 0.2 V
VSYM Output symmetry (dominant or recessive) (VO(CANH) + VO(CANL))/VCC See Figure 9-1 and Figure 9-4, 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open, C1 = 4.7nF, TXD = 250kHz, 1MHz, 2.5MHz 0.95 1.05 V/V
VSYM_DC Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended, <1 MHz or <2 Mbit/s See Figure 9-1 and Figure 9-4, 45Ω ≤ RL ≤ 65Ω, CL = open, RCM = open, C1 = 4.7nF –300 300 mV
IOS_DOM Short-circuit steady-state output current, dominant See Figure 9-1 and Figure 9-8  –3.0V ≤ VCANH ≤ +18.0V, CANL = open, VTXD = 0V –115 mA
 –3.0V ≤ VCANL ≤ +18.0 , CANH = open, VTXD = 0V 115 mA
IOS_REC Short-circuit steady-state output current, recessive. See Figure 9-1 and Figure 9-8  –27V ≤ VBUS ≤ +42V, VBUS = CANH = CANL –5 5 mA
RSE_ACT_REC Single ended SIC impedance (CANH  to common mode bias and CANL to common mode bias) during active recessive drive phase TXD= 0V, 2V ≤ VO(D) ≤ VCC - 2V if
–12V ≤ VO(D) ≤ 12V
Use Delta V/ Delta I method(same as used for RSE_PAS_REC/RDIFF_PAS_REC in RX section), no load on bus		 37.5 66.5 Ω
RDIFF_ACT_REC Differential input resistance in active recessive drive phase (CANH to CANL) 2V ≤ VO(D) ≤ VCC - 2V

Duration from TXD= From low-to-high edge to elapse of active recessive drive period (tREC_START), Use Delta V/ Delta I method(same as used for RSE_PAS_REC/RDIFF_PAS_REC in RX section), no load on bus		 75 133 Ω
CAN RECEIVER ELECTRICAL CHARACTERISTICS
VITDOM Receiver dominant state differential input voltage range, bus biasing active –12V ≤ VCANL ≤ +12V
–12V ≤ VCANH ≤ +12V; See Figure 9-5 and Table 10-6  		 0.9 8 V
VITREC Receiver recessive state differential input voltage range, bus biasing active –3 0.5 V
VHYS Hysteresis voltage for input-threshold, normal and selective wake modes 135 mV
VDIFF_DOM Receiver dominant state differential input voltage range, bus biasing in-active 12V ≤ VCANL ≤ +12V
–12V ≤ VCANH ≤ +12V; See Figure 9-5 and Table 10-6  		 1.15 8 V
VDIFF_REC Receiver recessive state differential input voltage range, bus biasing in-active –3 0.4 V
VCM Common mode range: normal and standby mode –12 12 V
IIOFF(LKG) Power-off (unpowered) bus input leakage current CANH = CANL = 5V, VCC = VIO = Vsup to GND via 0Ω and 47kΩ resistor –5 5 µA
CI Input capacitance to ground (CANH or CANL)(1)  40 pF
CID Differential input capacitance(1)  20 pF
RDIFF_PAS_REC Differential input resistance during passive recessive phase VTXD = VIO, normal mode: –2V ≤ VCANH ≤ +7V;
–2V ≤ VCANL ≤ +7V		 12 100 kΩ
RSE_CANH/L Single ended Input resistance during passive recessive phase (CANH or CANL) –2V ≤ VCANH ≤ +7V
–2V ≤ VCANL ≤ +7V		 6 50 kΩ
RIN(M) Input resistance matching: [2 x (RIN(CANH - RINCANL)/(RCANH+RINCANL)] VCANH = VCANL = 5V –1 1 %
INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT)
ΔVH High-level voltage drop from VSUP to INH  IINH = –6mA 0.5 1 V
Rpd Pull-down resistor Sleep Mode 7 10 13 MΩ
WAKE INPUT TERMINAL
VIH High-level input voltage Selective wake-up or standby mode, WAKE pin enabled 4 V
VIL Low-level input voltage Selective wake-up or standby mode, WAKE pin enabled 2 V
IIL Low-level input current WAKE = 1V 1 2 µA
SDI, SCK, nCS, TXD INPUT TERMINALS
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current 1.71V ≤ VIO ≤ 5.5V –1 1 µA
IIL Low-level input leakage current Inputs = 0V, 1.71V ≤ VIO ≤ 5.5V –30 –2 µA
CIN Input capacitance at 20MHz 2 15 pF
ILKG(OFF) Unpowered leakage current Inputs = 5.5V, VIO = VSUP = 0V –1 0 1 µA
Rpu Pull-up resistor 250 350 450 kΩ
RXD, SDO OUTPUT TERMINALS
VOH High level output voltage IOH = -2mA 0.8 VIO
VOL Low level output voltage IOL = 2mA 0.2 VIO
ILKG(OFF) Unpowered leakage current - SDO pin VnCS = VIO; VO = 0V to VIO –5 5 µA
RRXD(PU) RXD pin pull-up resistance Active during UVSUP and POR conditions and when in Sleep mode 40 60 80 kΩ
ILKG(RXD) RXD current when VIO present and RRXD(PU) enabled VRXD = VIO; VO = 0V to VIO –1 1 µA
VRXD = GND; Active during UVSUP and POR conditions and when in Sleep mode –140 –20 µA
(1) Test according to ISO 11898-2:2024
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