8.1 Overview

The TCAN4550 is a CAN FD controller with an integrated CAN FD transceiver supporting data rates up to 5 Mbps. The CAN FD controller meets the specifications of the ISO 11898-1:2015 high speed Controller Area Network (CAN) data link layer and meets the physical layer requirements of the ISO 11898-2:2016 High Speed Controller Area Network (CAN) specification providing an interface between the CAN bus and the CAN protocol controller supporting both classical CAN and CAN FD up to 5 megabits per second (Mbps). The TCAN4550 provides CAN FD transceiver functionality: differential transmit capability to the bus and differential receive capability from the bus. The device includes many protection features providing device and CAN bus robustness. The device can also wake up via remote wake up using CAN bus implementing the ISO 11898-2:2016 Wake Up Pattern (WUP). Input/Output support for 3.3 V and 5 V microprocessors using V_IO pin for seamless interface. The TCAN4550 has a Serial Peripheral Interface (SPI) that connects to a local microprocessor for the device's configuration; transmission and reception of CAN frames. The SPI interface supports clock rates up to 18 MHz.

The CAN bus has two logical states during operation: recessive and dominant. See Figure 3 and Figure 4.

In the recessive bus state, the bus is biased to a common mode of 2.5 V via the high resistance internal input resistors of the receiver of each node. Recessive is equivalent to logic high. The recessive state is also the idle state.

In the dominant bus state, the bus is driven differentially by one or more drivers. Current flows through the termination resistors and generates a differential voltage on the bus. Dominant is equivalent to logic low. A dominant state overwrites the recessive state.

During arbitration, multiple CAN nodes may transmit a dominant bit at the same time. In this case, the differential voltage of the bus is greater than the differential voltage of a single driver.

Transceivers with low power Standby Mode have a third bus state where the bus terminals are weakly biased to ground via the high resistance internal resistors of the receiver. See Figure 3 and Figure 4. The TCAN4550 supports auto biasing, see CAN Bus Biasing

The TCAN4550 has the ability to provide a single-ended clock output (GPIO1) based upon the crystal or single-ended clock input on OSC1.Many of the pins can be configured for multiple purposes and are described in more detail in Feature Description section. Much of the parametric data is based on internal links like the TXD/RXD_INT which represent the TXD and RXD of a standalone CAN transceiver. The TCAN4550 has a test mode that maps these signals to an external pin in order to perform compliance testing on the transceiver (TXD/RXD_INT_PHY) and CAN core (TXD/RXD_INT_CAN) independently.