ZHCSJ34F December   2015  – May 2019 TDA2HF , TDA2HG , TDA2HV , TDA2LF , TDA2SA , TDA2SG , TDA2SX

PRODUCTION DATA.  

  1. 1 器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2 修订历史记录
  3. 3 Device Comparison
    1. 3.1 Related Products
  4. 4 Terminal Configuration and Functions
    1. 4.1 Terminal Assignment
      1. 4.1.1 Unused Balls Connection Requirements
    2. 4.2 Ball Characteristics
    3. 4.3 Multiplexing Characteristics
    4. 4.4 Signal Descriptions
      1. 4.4.1  Video Input Port (VIP)
      2. 4.4.2  Display Subsystem – Video Output Ports
      3. 4.4.3  Display Subsystem – High-Definition Multimedia Interface (HDMI)
      4. 4.4.4  External Memory Interface (EMIF)
      5. 4.4.5  General-Purpose Memory Controller (GPMC)
      6. 4.4.6  Timers
      7. 4.4.7  Inter-Integrated Circuit Interface (I2C)
      8. 4.4.8  Universal Asynchronous Receiver Transmitter (UART)
      9. 4.4.9  Multichannel Serial Peripheral Interface (McSPI)
      10. 4.4.10 Quad Serial Peripheral Interface (QSPI)
      11. 4.4.11 Multichannel Audio Serial Port (McASP)
      12. 4.4.12 Universal Serial Bus (USB)
      13. 4.4.13 SATA
      14. 4.4.14 Peripheral Component Interconnect Express (PCIe)
      15. 4.4.15 Controller Area Network Interface (DCAN)
      16. 4.4.16 Ethernet Interface (GMAC_SW)
      17. 4.4.17 eMMC/SD/SDIO
      18. 4.4.18 General-Purpose Interface (GPIO)
      19. 4.4.19 Pulse Width Modulation (PWM) Interface
      20. 4.4.20 System and Miscellaneous
        1. 4.4.20.1 Sysboot Interface
        2. 4.4.20.2 Power, Reset, and Clock Management (PRCM)
        3. 4.4.20.3 Real Time Clock (RTC) Interface
        4. 4.4.20.4 System Direct Memory Access (SDMA)
        5. 4.4.20.5 Interrupt Controllers (INTC)
        6. 4.4.20.6 Observability
        7. 4.4.20.7 Power Supplies
      21. 4.4.21 Test Interfaces
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power on Hour (POH) Limits
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6 Power Consumption Summary
    7. 5.7 Electrical Characteristics
      1. 5.7.1  LVCMOS DDR DC Electrical Characteristics
      2. 5.7.2  HDMIPHY DC Electrical Characteristics
      3. 5.7.3  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      4. 5.7.4  IQ1833 Buffers DC Electrical Characteristics
      5. 5.7.5  IHHV1833 Buffers DC Electrical Characteristics
      6. 5.7.6  LVCMOS OSC Buffers DC Electrical Characteristics
      7. 5.7.7  BC1833IHHV Buffers DC Electrical Characteristics
      8. 5.7.8  USBPHY DC Electrical Characteristics
      9. 5.7.9  Dual Voltage SDIO1833 DC Electrical Characteristics
      10. 5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics
      11. 5.7.11 SATAPHY DC Electrical Characteristics
      12. 5.7.12 PCIEPHY DC Electrical Characteristics
    8. 5.8 Thermal Resistance Characteristics
      1. 5.8.1 Package Thermal Characteristics
    9. 5.9 Power Supply Sequences
  6. 6 Clock Specifications
    1. 6.1 Input Clock Specifications
      1. 6.1.1 Input Clock Requirements
      2. 6.1.2 System Oscillator OSC0 Input Clock
        1. 6.1.2.1 OSC0 External Crystal
        2. 6.1.2.2 OSC0 Input Clock
      3. 6.1.3 Auxiliary Oscillator OSC1 Input Clock
        1. 6.1.3.1 OSC1 External Crystal
        2. 6.1.3.2 OSC1 Input Clock
      4. 6.1.4 RTC Oscillator Input Clock
        1. 6.1.4.1 RTC Oscillator External Crystal
        2. 6.1.4.2 RTC Oscillator Input Clock
    2. 6.2 RC On-die Oscillator Clock
    3. 6.3 DPLLs, DLLs Specifications
      1. 6.3.1 DPLL Characteristics
      2. 6.3.2 DLL Characteristics
      3. 6.3.3 DPLL and DLL Noise Isolation
  7. 7 Timing Requirements and Switching Characteristics
    1. 7.1  Timing Test Conditions
    2. 7.2  Interface Clock Specifications
      1. 7.2.1 Interface Clock Terminology
      2. 7.2.2 Interface Clock Frequency
    3. 7.3  Timing Parameters and Information
      1. 7.3.1 Parameter Information
        1. 7.3.1.1 1.8V and 3.3V Signal Transition Levels
        2. 7.3.1.2 1.8V and 3.3V Signal Transition Rates
        3. 7.3.1.3 Timing Parameters and Board Routing Analysis
    4. 7.4  Recommended Clock and Control Signal Transition Behavior
    5. 7.5  Virtual and Manual I/O Timing Modes
    6. 7.6  Video Input Ports (VIP)
    7. 7.7  Display Subsystem – Video Output Ports
    8. 7.8  Display Subsystem – High-Definition Multimedia Interface (HDMI)
    9. 7.9  External Memory Interface (EMIF)
    10. 7.10 General-Purpose Memory Controller (GPMC)
      1. 7.10.1 GPMC/NOR Flash Interface Synchronous Timing
      2. 7.10.2 GPMC/NOR Flash Interface Asynchronous Timing
      3. 7.10.3 GPMC/NAND Flash Interface Asynchronous Timing
    11. 7.11 Timers
    12. 7.12 Inter-Integrated Circuit Interface (I2C)
      1. Table 7-34 Timing Requirements for I2C Input Timings
      2. Table 7-35 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
      3. Table 7-36 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
    13. 7.13 Universal Asynchronous Receiver Transmitter (UART)
      1. Table 7-37 Timing Requirements for UART
      2. Table 7-38 Switching Characteristics Over Recommended Operating Conditions for UART
    14. 7.14 Multichannel Serial Peripheral Interface (McSPI)
    15. 7.15 Quad Serial Peripheral Interface (QSPI)
    16. 7.16 Multichannel Audio Serial Port (McASP)
      1. Table 7-45 Timing Requirements for McASP1
      2. Table 7-46 Timing Requirements for McASP2
      3. Table 7-47 Timing Requirements for McASP3/4/5/6/7/8
      4. Table 7-48 Switching Characteristics Over Recommended Operating Conditions for McASP1
      5. Table 7-49 Switching Characteristics Over Recommended Operating Conditions for McASP2
      6. Table 7-50 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
    17. 7.17 Universal Serial Bus (USB)
      1. 7.17.1 USB1 DRD PHY
      2. 7.17.2 USB2 PHY
      3. 7.17.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
    18. 7.18 Serial Advanced Technology Attachment (SATA)
    19. 7.19 Peripheral Component Interconnect Express (PCIe)
    20. 7.20 Controller Area Network Interface (DCAN)
      1. Table 7-65 Timing Requirements for DCANx Receive
      2. Table 7-66 Switching Characteristics Over Recommended Operating Conditions for DCANx Transmit
    21. 7.21 Ethernet Interface (GMAC_SW)
      1. 7.21.1 GMAC MII Timings
        1. Table 7-67 Timing Requirements for miin_rxclk - MII Operation
        2. Table 7-68 Timing Requirements for miin_txclk - MII Operation
        3. Table 7-69 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
        4. Table 7-70 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
      2. 7.21.2 GMAC MDIO Interface Timings
      3. 7.21.3 GMAC RMII Timings
        1. Table 7-75 Timing Requirements for GMAC REF_CLK - RMII Operation
        2. Table 7-76 Timing Requirements for GMAC RMIIn Receive
        3. Table 7-77 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
        4. Table 7-78 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
      4. 7.21.4 GMAC RGMII Timings
        1. Table 7-82 Timing Requirements for rgmiin_rxc - RGMIIn Operation
        2. Table 7-83 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
        3. Table 7-84 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
        4. Table 7-85 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
    22. 7.22 eMMC/SD/SDIO
      1. 7.22.1 MMC1—SD Card Interface
        1. 7.22.1.1 Default speed, 4-bit data, SDR, half-cycle
        2. 7.22.1.2 High speed, 4-bit data, SDR, half-cycle
        3. 7.22.1.3 SDR12, 4-bit data, half-cycle
        4. 7.22.1.4 SDR25, 4-bit data, half-cycle
        5. 7.22.1.5 UHS-I SDR50, 4-bit data, half-cycle
        6. 7.22.1.6 UHS-I SDR104, 4-bit data, half-cycle
        7. 7.22.1.7 UHS-I DDR50, 4-bit data
      2. 7.22.2 MMC2 — eMMC
        1. 7.22.2.1 Standard JC64 SDR, 8-bit data, half cycle
        2. 7.22.2.2 High-speed JC64 SDR, 8-bit data, half cycle
        3. 7.22.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
        4. 7.22.2.4 High-speed JC64 DDR, 8-bit data
      3. 7.22.3 MMC3 and MMC4—SDIO/SD
        1. 7.22.3.1 MMC3 and MMC4, SD Default Speed
        2. 7.22.3.2 MMC3 and MMC4, SD High Speed
        3. 7.22.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
        4. 7.22.3.4 MMC3 and MMC4, SD SDR25 Mode
        5. 7.22.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
    23. 7.23 General-Purpose Interface (GPIO)
    24. 7.24 System and Miscellaneous interfaces
    25. 7.25 Test Interfaces
      1. 7.25.1 IEEE 1149.1 Standard-Test-Access Port (JTAG)
        1. 7.25.1.1 JTAG Electrical Data/Timing
          1. Table 7-134 Timing Requirements for IEEE 1149.1 JTAG
          2. Table 7-135 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
          3. Table 7-136 Timing Requirements for IEEE 1149.1 JTAG With RTCK
          4. Table 7-137 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
      2. 7.25.2 Trace Port Interface Unit (TPIU)
        1. 7.25.2.1 TPIU PLL DDR Mode
  8. 8 Applications, Implementation, and Layout
    1. 8.1 Introduction
      1. 8.1.1 Initial Requirements and Guidelines
    2. 8.2 Power Optimizations
      1. 8.2.1 Step 1: PCB Stack-up
      2. 8.2.2 Step 2: Physical Placement
      3. 8.2.3 Step 3: Static Analysis
        1. 8.2.3.1 PDN Resistance and IR Drop
      4. 8.2.4 Step 4: Frequency Analysis
      5. 8.2.5 System ESD Generic Guidelines
        1. 8.2.5.1 System ESD Generic PCB Guideline
        2. 8.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 8.2.6 EMI / EMC Issues Prevention
        1. 8.2.6.1 Signal Bandwidth
        2. 8.2.6.2 Signal Routing
          1. 8.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 8.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 8.2.6.3 Ground Guidelines
          1. 8.2.6.3.1 PCB Outer Layers
          2. 8.2.6.3.2 Metallic Frames
          3. 8.2.6.3.3 Connectors
          4. 8.2.6.3.4 Guard Ring on PCB Edges
          5. 8.2.6.3.5 Analog and Digital Ground
    3. 8.3 Core Power Domains
      1. 8.3.1 General Constraints and Theory
      2. 8.3.2 Voltage Decoupling
      3. 8.3.3 Static PDN Analysis
      4. 8.3.4 Dynamic PDN Analysis
      5. 8.3.5 Power Supply Mapping
      6. 8.3.6 DPLL Voltage Requirement
      7. 8.3.7 Loss of Input Power Event
      8. 8.3.8 Example PCB Design
        1. 8.3.8.1 Example Stack-up
        2. 8.3.8.2 vdd_mpu Example Analysis
    4. 8.4 Single-Ended Interfaces
      1. 8.4.1 General Routing Guidelines
      2. 8.4.2 QSPI Board Design and Layout Guidelines
    5. 8.5 Differential Interfaces
      1. 8.5.1 General Routing Guidelines
      2. 8.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 8.5.2.1 Background
        2. 8.5.2.2 USB PHY Layout Guide
          1. 8.5.2.2.1 General Routing and Placement
          2. 8.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 8.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 8.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 8.5.2.2.2.3  Board Stackup
            4. 8.5.2.2.2.4  Cable Connector Socket
            5. 8.5.2.2.2.5  Clock Routings
            6. 8.5.2.2.2.6  Crystals/Oscillator
            7. 8.5.2.2.2.7  DP/DM Trace
            8. 8.5.2.2.2.8  DP/DM Vias
            9. 8.5.2.2.2.9  Image Planes
            10. 8.5.2.2.2.10 JTAG Interface
            11. 8.5.2.2.2.11 Power Regulators
        3. 8.5.2.3 Electrostatic Discharge (ESD)
          1. 8.5.2.3.1 IEC ESD Stressing Test
            1. 8.5.2.3.1.1 Test Mode
            2. 8.5.2.3.1.2 Air Discharge Mode
            3. 8.5.2.3.1.3 Test Type
          2. 8.5.2.3.2 TI Component Level IEC ESD Test
          3. 8.5.2.3.3 Construction of a Custom USB Connector
          4. 8.5.2.3.4 ESD Protection System Design Consideration
        4. 8.5.2.4 References
      3. 8.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 8.5.3.1 USB 3.0 interface introduction
        2. 8.5.3.2 USB 3.0 General routing rules
      4. 8.5.4 HDMI Board Design and Layout Guidelines
        1. 8.5.4.1 HDMI Interface Schematic
        2. 8.5.4.2 TMDS General Routing Guidelines
        3. 8.5.4.3 TPD5S115
        4. 8.5.4.4 HDMI ESD Protection Device (Required)
        5. 8.5.4.5 PCB Stackup Specifications
        6. 8.5.4.6 Grounding
      5. 8.5.5 SATA Board Design and Layout Guidelines
        1. 8.5.5.1 SATA Interface Schematic
        2. 8.5.5.2 Compatible SATA Components and Modes
        3. 8.5.5.3 PCB Stackup Specifications
        4. 8.5.5.4 Routing Specifications
      6. 8.5.6 PCIe Board Design and Layout Guidelines
        1. 8.5.6.1 PCIe Connections and Interface Compliance
          1. 8.5.6.1.1 Coupling Capacitors
          2. 8.5.6.1.2 Polarity Inversion
        2. 8.5.6.2 Non-standard PCIe connections
          1. 8.5.6.2.1 PCB Stackup Specifications
          2. 8.5.6.2.2 Routing Specifications
            1. 8.5.6.2.2.1 Impedance
            2. 8.5.6.2.2.2 Differential Coupling
            3. 8.5.6.2.2.3 Pair Length Matching
        3. 8.5.6.3 LJCB_REFN/P Connections
    6. 8.6 Clock Routing Guidelines
      1. 8.6.1 32-kHz Oscillator Routing
      2. 8.6.2 Oscillator Ground Connection
    7. 8.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 8.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 8.7.2 DDR2 Board Design and Layout Guidelines
        1. 8.7.2.1 Board Designs
        2. 8.7.2.2 DDR2 Interface
          1. 8.7.2.2.1  DDR2 Interface Schematic
          2. 8.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 8.7.2.2.3  PCB Stackup
          4. 8.7.2.2.4  Placement
          5. 8.7.2.2.5  DDR2 Keepout Region
          6. 8.7.2.2.6  Bulk Bypass Capacitors
          7. 8.7.2.2.7  High-Speed Bypass Capacitors
          8. 8.7.2.2.8  Net Classes
          9. 8.7.2.2.9  DDR2 Signal Termination
          10. 8.7.2.2.10 VREF Routing
        3. 8.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 8.7.3 DDR3 Board Design and Layout Guidelines
        1. 8.7.3.1  Board Designs
          1. 8.7.3.1.1 DDR3 versus DDR2
        2. 8.7.3.2  DDR3 EMIFs
        3. 8.7.3.3  DDR3 Device Combinations
        4. 8.7.3.4  DDR3 Interface Schematic
          1. 8.7.3.4.1 32-Bit DDR3 Interface
          2. 8.7.3.4.2 16-Bit DDR3 Interface
        5. 8.7.3.5  Compatible JEDEC DDR3 Devices
        6. 8.7.3.6  PCB Stackup
        7. 8.7.3.7  Placement
        8. 8.7.3.8  DDR3 Keepout Region
        9. 8.7.3.9  Bulk Bypass Capacitors
        10. 8.7.3.10 High-Speed Bypass Capacitors
          1. 8.7.3.10.1 Return Current Bypass Capacitors
        11. 8.7.3.11 Net Classes
        12. 8.7.3.12 DDR3 Signal Termination
        13. 8.7.3.13 VREF_DDR Routing
        14. 8.7.3.14 VTT
        15. 8.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 8.7.3.15.1 Four DDR3 Devices
            1. 8.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 8.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 8.7.3.15.2 Two DDR3 Devices
            1. 8.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 8.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 8.7.3.15.3 One DDR3 Device
            1. 8.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 8.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 8.7.3.16 Data Topologies and Routing Definition
          1. 8.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 8.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 8.7.3.17 Routing Specification
          1. 8.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 8.7.3.17.2 DQS and DQ Routing Specification
  9. 9 Device and Documentation Support
    1. 9.1 Device Nomenclature and Orderable Information
      1. 9.1.1 Standard Package Symbolization
      2. 9.1.2 Device Naming Convention
    2. 9.2 Tools and Software
    3. 9.3 Documentation Support
    4. 9.4 Related Links
    5. 9.5 Community Resources
    6. 9.6 商标
    7. 9.7 静电放电警告
    8. 9.8 Glossary
  10. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Packaging Information

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ABC|760
散热焊盘机械数据 (封装 | 引脚)
订购信息

1.3 说明

TI 的全新 TDA2x 片上系统 (SoC) 是经过高度优化的可扩展系列器件，专为满足领先的高级驾驶员辅助系统 (ADAS) 的要求而设计。TDA2x 系列集最佳性能和低功耗特性于一体， 且其 ADAS 视觉分析处理功能有助于实现更自主的无碰撞驾驶体验，从而使其在汽车领域中的 ADAS 应用中得到了广泛的应用。

TDA2x SoC 通过最全面的 ADAS 应用 （包括前置摄像头、泊车辅助、环视和单一架构上的传感器融合），在汽车领域实现了复杂的嵌入式视觉技术。

TDA2x SoC 采用异构可扩展架构，包含 TI 的定点和浮点 TMS320C66x 数字信号处理器 (DSP) 生成内核、Vision AccelerationPac、 Arm®Cortex®-A15 MPCore™ 和双核 Cortex-M4 处理器。该器件集成了用于在以太网 AVB 网络上解码多视频流的视频加速器，以及用于渲染虚拟视图的图形加速器，因此可实现 3D 视觉体验。此外，TDA2x SoC 还集成了诸多外设，包括 LVDS 环视系统的多摄像头接口（并行和串行）、显示屏、CAN 和千兆位以太网 AVB。

适用于本系列米6体育平台手机版_好二三四的 Vision AccelerationPac 包含多个嵌入式视觉引擎 (EVE)，因此应用处理器不用再执行视觉分析功能，同时还降低了功耗。Vision AccelerationPac 针对视觉处理功能进行了优化，具有用于高效程序执行的 32 位 RISC 内核，以及用于专业视觉处理的矢量协处理器。

此外，TI 为 Arm、DSP 和 EVE 协处理器提供了一系列完整的开发工具，其中包括 C 语言编译器、用于简化编程和调度的 DSP 汇编优化器、可查看源代码执行情况的调试界面等。

TDA2x ADAS 处理器符合 AEC-Q100 标准。

器件信息(1)

器件型号 封装 封装尺寸
TDA2SXABC FCBGA (760) 23.0mm x 23.0mm
TDA2SGABC FCBGA (760) 23.0mm x 23.0mm
TDA2SAABC FCBGA (760) 23.0mm x 23.0mm
TDA2HGABC FCBGA (760) 23.0mm x 23.0mm
TDA2HVABC FCBGA (760) 23.0mm x 23.0mm
TDA2HFABC FCBGA (760) 23.0mm x 23.0mm
TDA2LFABC FCBGA (760) 23.0mm x 23.0mm
(1) 更多信息，请参阅，机械、封装和可订购信息。
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