ZHCSJ48F December 2016 – December 2018 TDA2P-ABZ
ADVANCE INFORMATION for pre-production products; subject to change without notice.
The device supports connections to PCIe-compliant devices via the integrated PCIe master/slave bus interface. The PCIe module is comprised of a dual-mode PCIe core and a SerDes PHY. Each PCIe subsystem controller has support for PCIe Gen-II mode (5.0 Gbps /lane) and Gen-I mode (2.5 Gbps/lane) (Single Lane and Flexible dual lane configuration).
The device PCIe supports the following features:
The PCIe controller on this device conforms to the PCI Express Base 3.0 Specification, revision 1.0 and the PCI Local Bus Specification, revision 3.0.
NOTE
For more information, see the PCIe Controller section of the Device TRM.