7.5.6.3 LJCB_REFN/P Connections

A Common Refclk Rx Architecture is required to be used for the device PCIe interface. Specifically, two modes of Common Refclk Rx Architecture are supported:

• External REFCLK Mode: An common external 100 MHz clock source is distributed to both the Device and the link partner
• Output REFCLK Mode: A 100 MHz HCSL clock source is output by the device and used by the link partner

In External REFCLK Mode, a high-quality, low-jitter, differential HCSL 100 MHz clock source compliant to the PCIe REFCLK AC Specifications should be provided on the Device’s ljcb_clkn / ljcb_clkp inputs. Alternatively, an LVDS clock source can be used with the following additional requirements:

• External AC coupling capacitors described in Table 7-26 should be populated at the ljcb_clkn / ljcb_clkp inputs.
• All termination requirements (ex. parallel 100 Ω termination) from the clock source manufacturer should be followed.

In Output REFCLK Mode, the 100 MHz clock from the Device’s DPLL_PCIE_REF should be output on the Device’s ljcb_clkn / ljcb_clkp pins and used as the HCSL REFCLK by the link partner. External near-side termination to ground described in Table 7-27 is required on both of the ljcb_clkn / ljcb_clkp outputs in this mode.

1. EIA LxW units, i.e., a 0402 is a 40×20 mils surface mount capacitor.
2. The physical size of the capacitor should be as small as practical. Use the same size on both lines in each pair placed side by side.