ZHCSJ49F March   2017  – February 2019 TDA2P-ACD

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 eMMC/SD/SDIO
      19. 4.3.19 GPIO
      20. 4.3.20 PWM
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Sysboot Interface
        2. 4.3.21.2 PRCM
        3. 4.3.21.3 SDMA
        4. 4.3.21.4 INTC
        5. 4.3.21.5 Observability
        6. 4.3.21.6 Power Supplies
      22. 4.3.22 Test Interfaces
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  LVCMOS CSI2 DC Electrical Characteristics
      5. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage SDIO1833 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. 5.7.1      HDMIPHY DC Electrical Characteristics
      9. 5.7.2      SATAPHY DC Electrical Characteristics
      10. 5.7.3      USBPHY DC Electrical Characteristics
      11. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-59 Timing Requirements for I2C Input Timings
          2. Table 5-60 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 UART
          1. Table 5-62 Timing Requirements for UART
          2. Table 5-63 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-70 Timing Requirements for McASP1
          2. Table 5-71 Timing Requirements for McASP2
          3. Table 5-72 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-74 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-75 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
          3. 5.10.6.14.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-90  Timing Requirements for CANx Receive
          4. Table 5-91  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-92 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-93 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-94 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-95 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-100 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-101 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-107 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-108 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-110 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High-Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High-Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 GPIO
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-159 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-160 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-161 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-162 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 Memory Subsystem
      1. 6.11.1 EMIF
      2. 6.11.2 GPMC
      3. 6.11.3 ELM
      4. 6.11.4 OCMC
    12. 6.12 Interprocessor Communication
      1. 6.12.1 Mailbox
      2. 6.12.2 Spinlock
    13. 6.13 Interrupt Controller
    14. 6.14 EDMA
    15. 6.15 Peripherals
      1. 6.15.1  VIP
      2. 6.15.2  DSS
      3. 6.15.3  Timers
      4. 6.15.4  I2C
      5. 6.15.5  UART
        1. 6.15.5.1 UART Features
        2. 6.15.5.2 IrDA Features
        3. 6.15.5.3 CIR Features
      6. 6.15.6  McSPI
      7. 6.15.7  QSPI
      8. 6.15.8  McASP
      9. 6.15.9  USB
      10. 6.15.10 SATA
      11. 6.15.11 PCIe
      12. 6.15.12 CAN
      13. 6.15.13 GMAC_SW
      14. 6.15.14 CSI2
        1. 6.15.14.1 CSI-2 MIPI D-PHY
      15. 6.15.15 eMMC/SD/SDIO
      16. 6.15.16 GPIO
      17. 6.15.17 ePWM
      18. 6.15.18 eCAP
      19. 6.15.19 eQEP
    16. 6.16 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
    6. 7.6 CSI2 Board Design and Routing Guidelines
      1. 7.6.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
        1. 7.6.1.1 General Guidelines
        2. 7.6.1.2 Length Mismatch Guidelines
          1. 7.6.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
        3. 7.6.1.3 Frequency-domain Specification Guidelines
    7. 7.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.7.3 DDR3 Board Design and Layout Guidelines
        1. 7.7.3.1  Board Designs
        2. 7.7.3.2  DDR3 EMIF
        3. 7.7.3.3  DDR3 Device Combinations
        4. 7.7.3.4  DDR3 Interface Schematic
          1. 7.7.3.4.1 32-Bit DDR3 Interface
          2. 7.7.3.4.2 16-Bit DDR3 Interface
        5. 7.7.3.5  Compatible JEDEC DDR3 Devices
        6. 7.7.3.6  PCB Stackup
        7. 7.7.3.7  Placement
        8. 7.7.3.8  DDR3 Keepout Region
        9. 7.7.3.9  Bulk Bypass Capacitors
        10. 7.7.3.10 High-Speed Bypass Capacitors
          1. 7.7.3.10.1 Return Current Bypass Capacitors
        11. 7.7.3.11 Net Classes
        12. 7.7.3.12 DDR3 Signal Termination
        13. 7.7.3.13 VREF_DDR Routing
        14. 7.7.3.14 VTT
        15. 7.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.3.15.1 Four DDR3 Devices
            1. 7.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.3.15.2 Two DDR3 Devices
            1. 7.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.3.15.3 One DDR3 Device
            1. 7.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.3.16 Data Topologies and Routing Definition
          1. 7.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.3.17 Routing Specification
          1. 7.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature and Orderable Information
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical Packaging Information
    1. 9.1 Mechanical Data

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.10.6.4 DSS

Three Display Parallel Interfaces (DPI) channels are available in DSS named DPI Video Output 1, DPI Video Output 2 and DPI Video Output 3.

NOTE

The DPI Video Output i (i = 1 to 3) interface is also referred to as VOUTi.

Every VOUT interface consists of:

  • 24-bit data bus (data[23:0])
  • Horizontal synchronization signal (HSYNC)
  • Vertical synchronization signal (VSYNC)
  • Data enable (DE)
  • Field ID (FID)
  • Pixel clock (CLK)

NOTE

For more information, see the Display Subsystem chapter of the Device TRM.

CAUTION

The I/O timings provided in this section are valid only if signals within a single IOSET are used. The IOSETs are defined in Table 5-44 and Table 5-45.

CAUTION

The I/O Timings provided in this section are valid only for some DSS usage modes when the corresponding Virtual I/O Timings or Manual I/O Timings are configured as described in the tables found in this section.

CAUTION

All pads/balls configured as vouti_* signals are recommended to use slow slew rate by setting the corresponding CTRL_CORE_PAD_*[SLEWCONTROL] register field to SLOW (0b1). FAST slew setting is allowed, but results in faster edge rates on the VOUTn bus, higher power/ground noise, and higher EMI emissions compared to SLOW slew rate.

Table 5-40, Table 5-41 and Figure 5-22 assume testing over the recommended operating conditions and electrical characteristic conditions.

Table 5-40 DPI Video Output i (i = 1..3) Default Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 11.76 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid -2.5 2.5 ns
D6 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid -2.5 2.5 ns
  1. P = output vouti_clk period in ns.
  2. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 5-41 DPI Video Output i (i = 1..3) Alternate Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 6.06 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid 1.51 4.55 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid 1.51 4.55 ns
  1. P = output vouti_clk period in ns.
  2. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 5-42 DPI Video Output i (i = 1..3) MANUAL3 Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 6.06 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid 2.85 5.56 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid 2.85 5.56 ns
  1. P = output vouti_clk period in ns.
  2. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.

Table 5-43 DPI Video Output i (i = 1..3) MANUAL4 Switching Characteristics

NO. PARAMETER DESCRIPTION MODE MIN MAX UNIT
D1 tc(clk) Cycle time, output pixel clock vouti_clk 6.06 (2) ns
D2 tw(clkL) Pulse duration, output pixel clock vouti_clk low P*0.5-1 (1) ns
D3 tw(clkH) Pulse duration, output pixel clock vouti_clk high P*0.5-1 (1) ns
D5 td(clk-ctlV) Delay time, output pixel clock vouti_clk transition to output data vouti_d[23:0] valid 3.55 6.61 ns
D6 td(clk-dV) Delay time, output pixel clock vouti_clk transition to output control signals vouti_vsync, vouti_hsync, vouti_de, and vouti_fld valid 3.55 6.61 ns
  1. P = output vouti_clk period in ns.
  2. SERDES transceivers may be sensitive to the jitter profile of vouti_clk. See Application Note SPRAC62 for additional guidance.
TDA2P-ACD SWPS049-018.gifFigure 5-22 DPI Video Output(1)(2)(3)
  1. The configuration of assertion of the data can be programmed on the falling or rising edge of the pixel clock.
  2. The polarity and the pulse width of vouti_hsync and vouti_vsync are programmable, refer to the DSS section of the Device TRM.
  3. The vouti_clk frequency can be configured, refer to the DSS section of the Device TRM.

NOTE

To configure the desired virtual mode the user must set MODESELECT bit and DELAYMODE bitfield for each corresponding pad control register.

The pad control registers are presentsed Table 4-29 and described in Device TRM, Control Module Chapter.

In Table 5-44 are presented the specific groupings of signals (IOSET) for use with VOUT2.

Table 5-44 VOUT2 IOSETs

SIGNALS IOSET1 IOSET2
BALL MUX BALL MUX
vout2_d23 F2 4 AA4 6
vout2_d22 E3 4 AB3 6
vout2_d21 E1 4 AB6 6
vout2_d20 E2 4 AA3 6
vout2_d19 D2 4 D17 6
vout2_d18 F3 4 D16 6
vout2_d17 D1 4 A20 6
vout2_d16 E4 4 C17 6
vout2_d15 G3 4 A16 6
vout2_d14 C5 4 B16 6
vout2_d13 D3 4 B15 6
vout2_d12 F4 4 D15 6
vout2_d11 E6 4 A14 6
vout2_d10 C1 4 B14 6
vout2_d9 C2 4 A19 6
vout2_d8 C3 4 E15 6
vout2_d7 B2 4 D12 6
vout2_d6 B5 4 C11 6
vout2_d5 D4 4 D13 6
vout2_d4 A3 4 E12 6
vout2_d3 B3 4 E11 6
vout2_d2 B4 4 E13 6
vout2_d1 C4 4 F14 6
vout2_d0 A4 4 A13 6
vout2_vsync E5 4 F17 6
vout2_hsync G1 4 E21 6
vout2_clk D5 4 B25 6
vout2_fld F1 4 F18 6
vout2_de G2 4 A22 6

In Table 5-45 are presented the specific groupings of signals (IOSET) for use with VOUT3.

Table 5-45 VOUT3 IOSETs

SIGNALS IOSET1 IOSET2 IOSET3
BALL MUX BALL MUX BALL MUX
vout3_d23 N6 3 AE9 4
vout3_d22 P5 3 AF10 4
vout3_d21 K4 3 AE7 4
vout3_d20 M6 3 AE8 4
vout3_d19 R5 3 AE6 4
vout3_d18 R4 3 AF7 4
vout3_d17 J6 3 AF8 4 AC9 3
vout3_d16 P6 3 AF6 4 AD8 3
vout3_d15 K3 3 AF4 4 AF4 4
vout3_d14 H2 3 AF2 4 AF2 4
vout3_d13 K2 3 AF3 4 AF3 4
vout3_d12 H1 3 AF5 4 AF5 4
vout3_d11 J2 3 AE5 4 AE5 4
vout3_d10 J1 3 AF1 4 AF1 4
vout3_d9 K1 3 AD6 4 AD6 4
vout3_d8 L1 3 AE3 4 AE3 4
vout3_d7 L2 3 AE4 4 AE9 3
vout3_d6 L3 3 AE1 4 AF10 3
vout3_d5 L4 3 AD5 4 AE7 3
vout3_d4 K6 3 AD3 4 AE8 3
vout3_d3 M1 3 AD4 4 AE6 3
vout3_d2 L5 3 AE2 4 AF7 3
vout3_d1 M2 3 AD1 4 AF8 3
vout3_d0 N5 3 AD2 4 AF6 3
vout3_de J5 3 AC9 4
vout3_vsync R3 3 AD7 4 AD7 4
vout3_clk P1 3 AD9 4 AD9 4
vout3_hsync N4 3 AC10 4 AC10 4
vout3_fld K5 3 AD8 4

NOTE

To configure the desired Manual IO Timing Mode the user must follow the steps described in section "Manual IO Timing Modes" of the Device TRM.

The associated registers to configure are listed in the CFG REGISTER column. For more information please see the Control Module Chapter in the Device TRM.

Manual IO Timings Modes must be used to guarantee some IO timings for VOUT1. See Table 5-28Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-46Manual Functions Mapping for DSS VOUT1 for a definition of the Manual modes.

Table 5-46 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-46 Manual Functions Mapping for DSS VOUT1

BALL BALL NAME VOUT1_MANUAL1 VOUT1_MANUAL2 VOUT1_MANUAL3 VOUT1_MANUAL4 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 0
D11 vout1_clk 0 29 1281 497 0 0 0 0 CFG_VOUT1_CLK_OUT vout1_clk
F9 vout1_d0 1878 0 379 0 3126 0 4185 0 CFG_VOUT1_D0_OUT vout1_d0
E10 vout1_d1 1978 0 475 0 3226 0 4284 0 CFG_VOUT1_D1_OUT vout1_d1
D6 vout1_d10 1943 0 441 0 3191 0 4249 0 CFG_VOUT1_D10_OUT vout1_d10
D7 vout1_d11 1964 0 461 0 3212 0 4271 0 CFG_VOUT1_D11_OUT vout1_d11
A5 vout1_d12 2726 0 1189 0 3974 0 5033 0 CFG_VOUT1_D12_OUT vout1_d12
B6 vout1_d13 1807 0 312 0 3055 0 4114 0 CFG_VOUT1_D13_OUT vout1_d13
C8 vout1_d14 1793 0 298 0 3041 0 4099 0 CFG_VOUT1_D14_OUT vout1_d14
C7 vout1_d15 1778 0 284 0 3026 0 4085 0 CFG_VOUT1_D15_OUT vout1_d15
B7 vout1_d16 1652 0 152 0 2887 0 3946 0 CFG_VOUT1_D16_OUT vout1_d16
B8 vout1_d17 1706 0 216 0 2954 0 4013 0 CFG_VOUT1_D17_OUT vout1_d17
A6 vout1_d18 1908 0 408 0 3156 0 4215 0 CFG_VOUT1_D18_OUT vout1_d18
A7 vout1_d19 2024 0 519 0 3272 0 4330 0 CFG_VOUT1_D19_OUT vout1_d19
D9 vout1_d2 1757 0 264 0 3005 0 4064 0 CFG_VOUT1_D2_OUT vout1_d2
C9 vout1_d20 1811 0 316 0 3059 0 4118 0 CFG_VOUT1_D20_OUT vout1_d20
A8 vout1_d21 1640 0 59 0 2814 0 3850 0 CFG_VOUT1_D21_OUT vout1_d21
B9 vout1_d22 1712 0 221 0 2960 0 4019 0 CFG_VOUT1_D22_OUT vout1_d22
A9 vout1_d23 1581 0 96 0 2829 0 3888 0 CFG_VOUT1_D23_OUT vout1_d23
C6 vout1_d3 1921 0 421 0 3169 0 4228 0 CFG_VOUT1_D3_OUT vout1_d3
E9 vout1_d4 2797 0 1257 0 4045 0 5104 0 CFG_VOUT1_D4_OUT vout1_d4
F8 vout1_d5 1933 0 432 0 3181 0 4240 0 CFG_VOUT1_D5_OUT vout1_d5
F7 vout1_d6 1937 0 436 0 3185 0 4244 0 CFG_VOUT1_D6_OUT vout1_d6
E7 vout1_d7 1941 0 440 0 3189 0 4248 0 CFG_VOUT1_D7_OUT vout1_d7
E8 vout1_d8 1701 0 81 100 2918 0 3977 0 CFG_VOUT1_D8_OUT vout1_d8
D8 vout1_d9 1973 0 471 0 3221 0 4280 0 CFG_VOUT1_D9_OUT vout1_d9
C10 vout1_de 1573 0 0 0 2747 0 3725 0 CFG_VOUT1_DE_OUT vout1_de
B10 vout1_fld 1709 0 224 0 2983 0 4004 0 CFG_VOUT1_FLD_OUT vout1_fld
A10 vout1_hsync 1514 0 0 0 2688 0 3666 0 CFG_VOUT1_HSYNC_OUT vout1_hsync
D10 vout1_vsync 2316 0 815 0 3564 0 4623 0 CFG_VOUT1_VSYNC_OUT vout1_vsync

Manual IO Timings Modes must be used to guarantee some IO timings for VOUT2. See Table 5-28, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-47, Manual Functions Mapping for DSS VOUT2 for a definition of the Manual modes.

Table 5-47 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-47 Manual Functions Mapping for DSS VOUT2 IOSET1

BALL BALL NAME VOUT2_IOSET1
_MANUAL1		 VOUT2_IOSET1
_MANUAL2		 VOUT2_IOSET1
_MANUAL3		 VOUT2_IOSET1
_MANUAL4		 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 4
F1 vin2a_clk0 2587 0 1178 0 3748 0 4694 0 CFG_VIN2A_CLK0_OUT vout2_fld
F2 vin2a_d0 2199 0 449 337 3360 0 4306 0 CFG_VIN2A_D0_OUT vout2_d23
E3 vin2a_d1 2141 0 731 0 3302 0 4248 0 CFG_VIN2A_D1_OUT vout2_d22
D3 vin2a_d10 1449 0 261 0 2810 0 3756 0 CFG_VIN2A_D10_OUT vout2_d13
F4 vin2a_d11 2010 0 425 181 3171 0 4117 0 CFG_VIN2A_D11_OUT vout2_d12
E6 vin2a_d12 2487 291 1649 73 3864 475 4680 605 CFG_VIN2A_D12_OUT vout2_d11
C1 vin2a_d13 2235 363 1594 148 3812 548 4629 677 CFG_VIN2A_D13_OUT vout2_d10
C2 vin2a_d14 2211 364 1456 167 3688 548 4504 678 CFG_VIN2A_D14_OUT vout2_d9
C3 vin2a_d15 2462 128 1542 0 3839 312 4656 441 CFG_VIN2A_D15_OUT vout2_d8
B2 vin2a_d16 2396 56 1554 0 3923 240 4740 370 CFG_VIN2A_D16_OUT vout2_d7
B5 vin2a_d17 2426 130 1510 0 3803 314 4620 444 CFG_VIN2A_D17_OUT vout2_d6
D4 vin2a_d18 2022 0 617 0 3183 0 4129 0 CFG_VIN2A_D18_OUT vout2_d5
A3 vin2a_d19 1826 0 430 0 2987 0 3933 0 CFG_VIN2A_D19_OUT vout2_d4
E1 vin2a_d2 1973 0 571 0 3134 0 4080 0 CFG_VIN2A_D2_OUT vout2_d21
B3 vin2a_d20 1514 0 110 0 2668 0 3618 0 CFG_VIN2A_D20_OUT vout2_d3
B4 vin2a_d21 1454 0 36 0 2608 0 3558 0 CFG_VIN2A_D21_OUT vout2_d2
C4 vin2a_d22 1432 0 0 0 2586 0 3536 0 CFG_VIN2A_D22_OUT vout2_d1
A4 vin2a_d23 1452 0 20 0 2606 0 3556 0 CFG_VIN2A_D23_OUT vout2_d0
E2 vin2a_d3 2007 0 603 0 3168 0 4114 0 CFG_VIN2A_D3_OUT vout2_d20
D2 vin2a_d4 2306 0 1366 0 3967 0 4913 0 CFG_VIN2A_D4_OUT vout2_d19
F3 vin2a_d5 2122 0 904 0 3483 0 4429 0 CFG_VIN2A_D5_OUT vout2_d18
D1 vin2a_d6 1867 0 660 0 3228 0 4174 0 CFG_VIN2A_D6_OUT vout2_d17
E4 vin2a_d7 1940 0 539 0 3101 0 4047 0 CFG_VIN2A_D7_OUT vout2_d16
G3 vin2a_d8 1752 0 359 0 2913 0 3859 0 CFG_VIN2A_D8_OUT vout2_d15
C5 vin2a_d9 1631 0 46 198 2792 0 3738 0 CFG_VIN2A_D9_OUT vout2_d14
G2 vin2a_de0 2136 0 726 0 3297 0 4243 0 CFG_VIN2A_DE0_OUT vout2_de
D5 vin2a_fld0 0 274 1409 698 0 161 0 55 CFG_VIN2A_FLD0_OUT vout2_clk
G1 vin2a_hsync0 2610 0 1200 0 3771 0 4717 0 CFG_VIN2A_HSYNC0_OUT vout2_hsync
E5 vin2a_vsync0 2214 0 822 0 3375 0 4321 0 CFG_VIN2A_VSYNC0_OUT vout2_vsync

Manual IO Timings Modes must be used to guarantee some IO timings for VOUT2. See Table 5-28, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-48, Manual Functions Mapping for DSS VOUT2 IOSET2 for a definition of the Manual modes.

Table 5-48 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-48 Manual Functions Mapping for DSS VOUT2 IOSET2

BALL BALL NAME VOUT2_IOSET2
_MANUAL1		 VOUT2_IOSET2
_MANUAL2		 VOUT2_IOSET2
_MANUAL3		 VOUT2_IOSET2
_MANUAL4		 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 6
E21 gpio6_14 1193 0 274 0 2474 0 3298 0 CFG_GPIO6_14_OUT vout2_hsync
F17 gpio6_15 1006 0 27 0 2226 0 3039 0 CFG_GPIO6_15_OUT vout2_vsync
F18 gpio6_16 921 0 0 0 2141 0 2955 0 CFG_GPIO6_16_OUT vout2_fld
A13 mcasp1_aclkr 3224 0 2192 0 4505 0 5328 0 CFG_MCASP1_ACLKR_OUT vout2_d0
E13 mcasp1_axr2 2197 0 1211 0 3478 0 4302 0 CFG_MCASP1_AXR2_OUT vout2_d2
E11 mcasp1_axr3 1989 0 1013 0 3271 0 4094 0 CFG_MCASP1_AXR3_OUT vout2_d3
E12 mcasp1_axr4 2452 0 1455 0 3733 0 4557 0 CFG_MCASP1_AXR4_OUT vout2_d4
D13 mcasp1_axr5 2507 0 1507 0 3788 0 4612 0 CFG_MCASP1_AXR5_OUT vout2_d5
C11 mcasp1_axr6 2212 0 1225 0 3493 0 4316 0 CFG_MCASP1_AXR6_OUT vout2_d6
D12 mcasp1_axr7 2204 0 1218 0 3485 0 4309 0 CFG_MCASP1_AXR7_OUT vout2_d7
F14 mcasp1_fsr 1933 0 959 0 3214 0 4037 0 CFG_MCASP1_FSR_OUT vout2_d1
E15 mcasp2_aclkr 3074 0 2048 0 4355 0 5178 0 CFG_MCASP2_ACLKR_OUT vout2_d8
B14 mcasp2_axr0 1798 0 830 0 3080 0 3903 0 CFG_MCASP2_AXR0_OUT vout2_d10
A14 mcasp2_axr1 2031 0 542 510 3312 0 4135 0 CFG_MCASP2_AXR1_OUT vout2_d11
D15 mcasp2_axr4 2050 0 1071 0 3331 0 4155 0 CFG_MCASP2_AXR4_OUT vout2_d12
B15 mcasp2_axr5 1627 0 667 0 2908 0 3732 0 CFG_MCASP2_AXR5_OUT vout2_d13
B16 mcasp2_axr6 2924 0 1905 0 4205 0 5028 0 CFG_MCASP2_AXR6_OUT vout2_d14
A16 mcasp2_axr7 1555 0 598 0 2836 0 3660 0 CFG_MCASP2_AXR7_OUT vout2_d15
A19 mcasp2_fsr 1689 0 188 539 2971 0 3794 0 CFG_MCASP2_FSR_OUT vout2_d9
C17 mcasp4_aclkx 2607 0 1603 0 3889 0 4712 0 CFG_MCASP4_ACLKX_OUT vout2_d16
D16 mcasp4_axr0 1690 0 727 0 2971 0 3795 0 CFG_MCASP4_AXR0_OUT vout2_d18
D17 mcasp4_axr1 1408 0 457 0 2689 0 3512 0 CFG_MCASP4_AXR1_OUT vout2_d19
A20 mcasp4_fsx 1564 0 606 0 2845 0 3668 0 CFG_MCASP4_FSX_OUT vout2_d17
AA3 mcasp5_aclkx 4355 1633 3732 1100 5399 1869 6062 2030 CFG_MCASP5_ACLKX_OUT vout2_d20
AB3 mcasp5_axr0 4307 1362 3675 853 5352 1599 6014 1759 CFG_MCASP5_AXR0_OUT vout2_d22
AA4 mcasp5_axr1 4276 971 3633 492 5321 1208 5984 1369 CFG_MCASP5_AXR1_OUT vout2_d23
AB6 mcasp5_fsx 4272 981 3628 503 5317 1217 5980 1378 CFG_MCASP5_FSX_OUT vout2_d21
B25 xref_clk2 0 51 2016 507 0 0 0 0 CFG_XREF_CLK2_OUT vout2_clk
A22 xref_clk3 2331 0 1339 0 3612 0 4436 0 CFG_XREF_CLK3_OUT vout2_de

Manual IO Timings Modes must be used to guarantee some IO timings for VOUT3. See Table 5-28, Modes Summary for a list of IO timings requiring the use of Manual IO Timings Modes. See Table 5-49, Manual Functions Mapping for DSS VOUT3 for a definition of the Manual modes.

Table 5-49 lists the A_DELAY and G_DELAY values needed to calculate the correct values to be set in the CFG_x registers.

Table 5-49 Manual Functions Mapping for DSS VOUT3

BALL BALL NAME VOUT3_MANUAL1 VOUT3_MANUAL2 VOUT3_MANUAL3 VOUT3_MANUAL4 CFG REGISTER MUXMODE
A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) A_DELAY (ps) G_DELAY (ps) 3 4
P6 gpmc_a0 1627 0 787 0 2798 0 3781 0 CFG_GPMC_A0_OUT vout3_d16 -
J6 gpmc_a1 1527 0 592 0 2698 0 3680 0 CFG_GPMC_A1_OUT vout3_d17 -
J5 gpmc_a10 1907 0 1181 0 3122 0 4194 0 CFG_GPMC_A10_OUT vout3_de -
K5 gpmc_a11 2406 0 1676 0 3622 0 4693 0 CFG_GPMC_A11_OUT vout3_fld -
R4 gpmc_a2 1508 0 641 0 2679 0 3661 0 CFG_GPMC_A2_OUT vout3_d18 -
R5 gpmc_a3 2222 0 1481 0 3437 0 4508 0 CFG_GPMC_A3_OUT vout3_d19 -
M6 gpmc_a4 2529 0 1775 0 3744 0 4815 0 CFG_GPMC_A4_OUT vout3_d20 -
K4 gpmc_a5 1492 0 785 0 2708 0 3779 0 CFG_GPMC_A5_OUT vout3_d21 -
P5 gpmc_a6 1578 0 848 0 2774 0 3845 0 CFG_GPMC_A6_OUT vout3_d22 -
N6 gpmc_a7 1586 0 851 0 2778 0 3849 0 CFG_GPMC_A7_OUT vout3_d23 -
N4 gpmc_a8 2519 0 1783 0 3734 0 4805 0 CFG_GPMC_A8_OUT vout3_hsync -
R3 gpmc_a9 1886 0 951 0 2864 0 3935 0 CFG_GPMC_A9_OUT vout3_vsync -
N5 gpmc_ad0 1813 0 1091 0 3028 0 4099 0 CFG_GPMC_AD0_OUT vout3_d0 -
M2 gpmc_ad1 1652 0 937 0 2868 0 3939 0 CFG_GPMC_AD1_OUT vout3_d1 -
J1 gpmc_ad10 1746 0 1027 0 2962 0 4033 0 CFG_GPMC_AD10_OUT vout3_d10 -
J2 gpmc_ad11 1534 0 824 0 2749 0 3820 0 CFG_GPMC_AD11_OUT vout3_d11 -
H1 gpmc_ad12 1923 0 1196 0 3138 0 4209 0 CFG_GPMC_AD12_OUT vout3_d12 -
K2 gpmc_ad13 1496 0 754 0 2676 0 3747 0 CFG_GPMC_AD13_OUT vout3_d13 -
H2 gpmc_ad14 1379 0 665 0 2582 0 3653 0 CFG_GPMC_AD14_OUT vout3_d14 -
K3 gpmc_ad15 1746 0 1027 0 2961 0 4032 0 CFG_GPMC_AD15_OUT vout3_d15 -
L5 gpmc_ad2 1894 0 1168 0 3110 0 4181 0 CFG_GPMC_AD2_OUT vout3_d2 -
M1 gpmc_ad3 1584 0 872 0 2800 0 3871 0 CFG_GPMC_AD3_OUT vout3_d3 -
K6 gpmc_ad4 1815 0 1092 0 3030 0 4101 0 CFG_GPMC_AD4_OUT vout3_d4 -
L4 gpmc_ad5 1436 0 576 0 2607 0 3589 0 CFG_GPMC_AD5_OUT vout3_d5 -
L3 gpmc_ad6 1837 0 1113 0 3052 0 4123 0 CFG_GPMC_AD6_OUT vout3_d6 -
L2 gpmc_ad7 1658 0 943 0 2874 0 3945 0 CFG_GPMC_AD7_OUT vout3_d7 -
L1 gpmc_ad8 515 0 0 0 1686 0 2757 0 CFG_GPMC_AD8_OUT vout3_d8 -
K1 gpmc_ad9 853 0 0 0 2024 0 3006 0 CFG_GPMC_AD9_OUT vout3_d9 -
P1 gpmc_cs3 0 234 1801 948 0 167 0 177 CFG_GPMC_CS3_OUT vout3_clk -
AD8 vin1a_clk0 1954 0 1244 0 3240 0 4298 0 CFG_VIN1A_CLK0_OUT vout3_d16 vout3_fld
AE9 vin1a_d0 1991 0 1261 0 3277 0 4336 0 CFG_VIN1A_D0_OUT vout3_d7 vout3_d23
AF10 vin1a_d1 1911 0 1185 0 3197 0 4256 0 CFG_VIN1A_D1_OUT vout3_d6 vout3_d22
AF3 vin1a_d10 2460 0 1647 0 3754 0 4813 0 CFG_VIN1A_D10_OUT - vout3_d13
AF5 vin1a_d11 2098 0 1302 0 3392 0 4451 0 CFG_VIN1A_D11_OUT - vout3_d12
AE5 vin1a_d12 2703 0 1880 0 3997 0 5056 0 CFG_VIN1A_D12_OUT - vout3_d11
AF1 vin1a_d13 2049 0 1255 0 3343 0 4402 0 CFG_VIN1A_D13_OUT - vout3_d10
AD6 vin1a_d14 2815 0 1987 0 4109 0 5131 37 CFG_VIN1A_D14_OUT - vout3_d9
AE3 vin1a_d15 1973 0 1183 0 3267 0 4326 0 CFG_VIN1A_D15_OUT - vout3_d8
AE4 vin1a_d16 2084 0 1289 0 3379 0 4437 0 CFG_VIN1A_D16_OUT - vout3_d7
AE1 vin1a_d17 2100 0 1304 0 3394 0 4453 0 CFG_VIN1A_D17_OUT - vout3_d6
AD5 vin1a_d18 2069 0 1274 0 3363 0 4422 0 CFG_VIN1A_D18_OUT - vout3_d5
AD3 vin1a_d19 2171 0 1372 0 3465 0 4524 0 CFG_VIN1A_D19_OUT - vout3_d4
AE7 vin1a_d2 1956 0 1227 0 3241 0 4300 0 CFG_VIN1A_D2_OUT vout3_d5 vout3_d21
AD4 vin1a_d20 2251 0 1448 0 3546 0 4604 0 CFG_VIN1A_D20_OUT - vout3_d3
AE2 vin1a_d21 2252 0 1449 0 3546 0 4605 0 CFG_VIN1A_D21_OUT - vout3_d2
AD1 vin1a_d22 2199 0 1187 211 3494 0 4552 0 CFG_VIN1A_D22_OUT - vout3_d1
AD2 vin1a_d23 2316 0 1510 0 3610 0 4669 0 CFG_VIN1A_D23_OUT - vout3_d0
AE8 vin1a_d3 2053 0 1320 0 3338 0 4397 0 CFG_VIN1A_D3_OUT vout3_d4 vout3_d20
AE6 vin1a_d4 2760 0 1995 0 4045 0 5015 89 CFG_VIN1A_D4_OUT vout3_d3 vout3_d19
AF7 vin1a_d5 1755 0 1007 0 3010 0 4069 0 CFG_VIN1A_D5_OUT vout3_d2 vout3_d18
AF8 vin1a_d6 1948 0 1220 0 3233 0 4292 0 CFG_VIN1A_D6_OUT vout3_d1 vout3_d17
AF6 vin1a_d7 1925 0 1198 0 3211 0 4270 0 CFG_VIN1A_D7_OUT vout3_d0 vout3_d16
AF4 vin1a_d8 2104 0 1307 0 3398 0 4457 0 CFG_VIN1A_D8_OUT - vout3_d15
AF2 vin1a_d9 2192 0 1392 0 3487 0 4545 0 CFG_VIN1A_D9_OUT - vout3_d14
AC9 vin1a_de0 2202 0 1462 0 3487 0 4546 0 CFG_VIN1A_DE0_OUT vout3_d17 vout3_de
AD9 vin1a_fld0 0 0 2007 454 0 0 0 0 CFG_VIN1A_FLD0_OUT - vout3_clk
AC10 vin1a_hsync0 2015 0 1240 0 3309 0 4367 0 CFG_VIN1A_HSYNC0_OUT - vout3_hsync
AD7 vin1a_vsync0 1829 0 1063 0 3123 0 4182 0 CFG_VIN1A_VSYNC0_OUT - vout3_vsync
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