ZHCSJ49F March   2017  – February 2019 TDA2P-ACD

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 eMMC/SD/SDIO
      19. 4.3.19 GPIO
      20. 4.3.20 PWM
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Sysboot Interface
        2. 4.3.21.2 PRCM
        3. 4.3.21.3 SDMA
        4. 4.3.21.4 INTC
        5. 4.3.21.5 Observability
        6. 4.3.21.6 Power Supplies
      22. 4.3.22 Test Interfaces
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  LVCMOS CSI2 DC Electrical Characteristics
      5. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage SDIO1833 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. 5.7.1      HDMIPHY DC Electrical Characteristics
      9. 5.7.2      SATAPHY DC Electrical Characteristics
      10. 5.7.3      USBPHY DC Electrical Characteristics
      11. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-59 Timing Requirements for I2C Input Timings
          2. Table 5-60 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 UART
          1. Table 5-62 Timing Requirements for UART
          2. Table 5-63 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-70 Timing Requirements for McASP1
          2. Table 5-71 Timing Requirements for McASP2
          3. Table 5-72 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-74 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-75 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
          3. 5.10.6.14.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-90  Timing Requirements for CANx Receive
          4. Table 5-91  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-92 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-93 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-94 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-95 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-100 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-101 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-107 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-108 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-110 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High-Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High-Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 GPIO
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-159 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-160 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-161 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-162 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 Memory Subsystem
      1. 6.11.1 EMIF
      2. 6.11.2 GPMC
      3. 6.11.3 ELM
      4. 6.11.4 OCMC
    12. 6.12 Interprocessor Communication
      1. 6.12.1 Mailbox
      2. 6.12.2 Spinlock
    13. 6.13 Interrupt Controller
    14. 6.14 EDMA
    15. 6.15 Peripherals
      1. 6.15.1  VIP
      2. 6.15.2  DSS
      3. 6.15.3  Timers
      4. 6.15.4  I2C
      5. 6.15.5  UART
        1. 6.15.5.1 UART Features
        2. 6.15.5.2 IrDA Features
        3. 6.15.5.3 CIR Features
      6. 6.15.6  McSPI
      7. 6.15.7  QSPI
      8. 6.15.8  McASP
      9. 6.15.9  USB
      10. 6.15.10 SATA
      11. 6.15.11 PCIe
      12. 6.15.12 CAN
      13. 6.15.13 GMAC_SW
      14. 6.15.14 CSI2
        1. 6.15.14.1 CSI-2 MIPI D-PHY
      15. 6.15.15 eMMC/SD/SDIO
      16. 6.15.16 GPIO
      17. 6.15.17 ePWM
      18. 6.15.18 eCAP
      19. 6.15.19 eQEP
    16. 6.16 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
    6. 7.6 CSI2 Board Design and Routing Guidelines
      1. 7.6.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
        1. 7.6.1.1 General Guidelines
        2. 7.6.1.2 Length Mismatch Guidelines
          1. 7.6.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
        3. 7.6.1.3 Frequency-domain Specification Guidelines
    7. 7.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.7.3 DDR3 Board Design and Layout Guidelines
        1. 7.7.3.1  Board Designs
        2. 7.7.3.2  DDR3 EMIF
        3. 7.7.3.3  DDR3 Device Combinations
        4. 7.7.3.4  DDR3 Interface Schematic
          1. 7.7.3.4.1 32-Bit DDR3 Interface
          2. 7.7.3.4.2 16-Bit DDR3 Interface
        5. 7.7.3.5  Compatible JEDEC DDR3 Devices
        6. 7.7.3.6  PCB Stackup
        7. 7.7.3.7  Placement
        8. 7.7.3.8  DDR3 Keepout Region
        9. 7.7.3.9  Bulk Bypass Capacitors
        10. 7.7.3.10 High-Speed Bypass Capacitors
          1. 7.7.3.10.1 Return Current Bypass Capacitors
        11. 7.7.3.11 Net Classes
        12. 7.7.3.12 DDR3 Signal Termination
        13. 7.7.3.13 VREF_DDR Routing
        14. 7.7.3.14 VTT
        15. 7.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.3.15.1 Four DDR3 Devices
            1. 7.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.3.15.2 Two DDR3 Devices
            1. 7.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.3.15.3 One DDR3 Device
            1. 7.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.3.16 Data Topologies and Routing Definition
          1. 7.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.3.17 Routing Specification
          1. 7.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature and Orderable Information
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical Packaging Information
    1. 9.1 Mechanical Data

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing

CAUTION

The IO Timings provided in this section are only valid for some GPMC usage modes when the corresponding Virtual IO Timings or Manual IO Timings are configured as described in the tables found in this section.

Table 5-50 and Table 5-51 assume testing over the recommended operating conditions and electrical characteristic conditions below (see Figure 5-23, Figure 5-24, Figure 5-25, Figure 5-26, Figure 5-27, and Figure 5-28).

Table 5-50 GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Default

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F12 tsu(dV-clkH) Setup time, read gpmc_ad[15:0] valid before gpmc_clk high 1.9 ns
F13 th(clkH-dV) Hold time, read gpmc_ad[15:0] valid after gpmc_clk high 1 ns
F21 tsu(waitV-clkH) Setup time, gpmc_wait[1:0] valid before gpmc_clk high 1.9 ns
F22 th(clkH-waitV) Hold Time, gpmc_wait[1:0] valid after gpmc_clk high 1 ns

NOTE

Wait monitoring support is limited to a WaitMonitoringTime value > 0. For a full description of wait monitoring feature, see General-Purpose Memory Controller section in the Device TRM.

Table 5-51 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Default

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F0 tc(clk) Cycle time, output clock gpmc_clk period 11.3 ns
F2 td(clkH-nCSV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition F(6)-0.8 F(6)+3.17 ns
F3 td(clkH-nCSIV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid E(5)-0.8 E(5)+3.1 ns
F4 td(ADDV-clk) Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge B(2)-0.8 B(2)+3.43 ns
F5 td(clkH-ADDIV) Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid -0.8 ns
F6 td(nBEV-clk) Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge B(2)-3.8 B(2)+2.37 ns
F7 td(clkH-nBEIV) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid D(4)-0.4 D(4)+1.1 ns
F8 td(clkH-nADV) Delay time, gpmc_clk rising edge to gpmc_advn_ale transition G(7)-0.8 G(7)+3.1 ns
F9 td(clkH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid D(4)-0.8 D(4)+3.1 ns
F10 td(clkH-nOE) Delay time, gpmc_clk rising edge to gpmc_oen_ren transition H(8)-0.8 H(8)+2.45 ns
F11 td(clkH-nOEIV) Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid E(5)-0.8 E(5)+2.1 ns
F14 td(clkH-nWE) Delay time, gpmc_clk rising edge to gpmc_wen transition I(9)-0.8 I(9)+3.1 ns
F15 td(clkH-Data) Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition J(10)-1.1 J(10)+4.89 ns
F17 td(clkH-nBE) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition J(10)-1.1 J(10)+3.8 ns
F18 tw(nCSV) Pulse duration, gpmc_cs[7:0] low A(1) ns
F19 tw(nBEV) Pulse duration, gpmc_ben[1:0] low C(3) ns
F20 tw(nADVV) Pulse duration, gpmc_advn_ale low K(11) ns
F23 td(CLK-GPIO) Delay time, gpmc_clk transition to gpio6_16 transition 1.2 6.1 ns

Table 5-52 GPMC/NOR Flash Interface Timing Requirements - Synchronous Mode - Alternate

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F12 tsu(dV-clkH) Setup time, read gpmc_ad[15:0] valid before gpmc_clk high 3.56 ns
F13 th(clkH-dV) Hold time, read gpmc_ad[15:0] valid after gpmc_clk high 1.9 ns
F21 tsu(waitV-clkH) Setup time, gpmc_wait[1:0] valid before gpmc_clk high 3.1 ns
F22 th(clkH-waitV) Hold Time, gpmc_wait[1:0] valid after gpmc_clk high 1.9 ns

Table 5-53 GPMC/NOR Flash Interface Switching Characteristics - Synchronous Mode - Alternate

NO. PARAMETER DESCRIPTION MIN MAX UNIT
F0 tc(clk) Cycle time, output clock gpmc_clk period (12) 15.04 ns
F2 td(clkH-nCSV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] transition (14) F(6)-0.13 F(6)+6.1 ns
F3 td(clkH-nCSIV) Delay time, gpmc_clk rising edge to gpmc_cs[7:0] invalid (14) E(5)+0.7 E(5)+6.1 ns
F4 td(ADDV-clk) Delay time, gpmc_a[27:0] address bus valid to gpmc_clk first edge B(2)+0.21 B(2)+6.1 ns
F5 td(clkH-ADDIV) Delay time, gpmc_clk rising edge to gpmc_a[27:0] gpmc address bus invalid 0.7 ns
F6 td(nBEV-clk) Delay time, gpmc_ben[1:0] valid to gpmc_clk rising edge B(2)-4.9 B(2)+0.4 ns
F7 td(clkH-nBEIV) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] invalid D(4)-0.4 D(4)+4.9 ns
F8 td(clkH-nADV) Delay time, gpmc_clk rising edge to gpmc_advn_ale transition (14) G(7)+0.7 G(7)+6.1 ns
F9 td(clkH-nADVIV) Delay time, gpmc_clk rising edge to gpmc_advn_ale invalid (14) D(4)+0.7 D(4)+6.1 ns
F10 td(clkH-nOE) Delay time, gpmc_clk rising edge to gpmc_oen_ren transition (14) H(8)+0.42 H(8)+5.1 ns
F11 td(clkH-nOEIV) Delay time, gpmc_clk rising edge to gpmc_oen_ren invalid (14) E(5)+0.7 E(5)+5.1 ns
F14 td(clkH-nWE) Delay time, gpmc_clk rising edge to gpmc_wen transition (14) I(9)+0.46 I(9)+6.1 ns
F15 td(clkH-Data) Delay time, gpmc_clk rising edge to gpmc_ad[15:0] data bus transition J(10)-0.4 J(10)+4.9 ns
F17 td(clkH-nBE) Delay time, gpmc_clk rising edge to gpmc_ben[1:0] transition J(10)-0.4 J(10)+5.63 ns
F18 tw(nCSV) Pulse duration, gpmc_cs[7:0] low A(1) ns
F19 tw(nBEV) Pulse duration, gpmc_ben[1:0] low C(3) ns
F20 tw(nADVV) Pulse duration, gpmc_advn_ale low K(11) ns
F23 td(CLK-GPIO) Delay time, gpmc_clk transition to gpio6_16 transition (13) 0.96 6.1 ns
  1. For single read: A = (CSRdOffTime - CSOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
    For burst read: A = (CSRdOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period
    For burst write: A = (CSWrOffTime - CSOnTime + (n - 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK period with n the page burst access number.
  2. B = ClkActivationTime × GPMC_FCLK
  3. For single read: C = RdCycleTime × (TimeParaGranularity + 1) × GPMC_FCLK
    For burst read: C = (RdCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
    For Burst write: C = (WrCycleTime + (n – 1) × PageBurstAccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK with n the page burst access number.
  4. For single read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
    For burst read: D = (RdCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
    For burst write: D = (WrCycleTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
  5. For single read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
    For burst read: E = (CSRdOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
    For burst write: E = (CSWrOffTime – AccessTime) × (TimeParaGranularity + 1) × GPMC_FCLK
  6. For nCS falling edge (CS activated):
    Case GpmcFCLKDivider = 0 :
    F = 0.5 × CSExtraDelay × GPMC_FCLK Case GpmcFCLKDivider = 1:
    F = 0.5 × CSExtraDelay × GPMC_FCLK if (ClkActivationTime and CSOnTime are odd) or (ClkActivationTime and CSOnTime are even)
    F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime – ClkActivationTime) is a multiple of 3)
    F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 1) is a multiple of 3)
    F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    F = 0.5 × CSExtraDelay × GPMC_FCLK if ((CSOnTime - ClkActivationTime) is a multiple of 4)
    F = (1 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 1) is a multiple of 4)
    F = (2 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 2) is a multiple of 4)
    F = (3 + 0.5 × CSExtraDelay) × GPMC_FCLK if ((CSOnTime - ClkActivationTime - 3) is a multiple of 4)
  7. For ADV falling edge (ADV activated):
    Case GpmcFCLKDivider = 0 :
    G = 0.5 × ADVExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVOnTime are odd) or (ClkActivationTime and ADVOnTime are even)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVOnTime – ClkActivationTime) is a multiple of 3)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 1) is a multiple of 3)
    G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVOnTime – ClkActivationTime – 2) is a multiple of 3)
    For ADV rising edge (ADV deactivated) in Reading mode:
    Case GpmcFCLKDivider = 0:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVRdOffTime are odd) or (ClkActivationTime and ADVRdOffTime are even)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 3)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 3)
    G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime) is a multiple of 4)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 1) is a multiple of 4)
    G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 2) is a multiple of 4)
    G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVRdOffTime – ClkActivationTime – 3) is a multiple of 4)
    For ADV rising edge (ADV deactivated) in Writing mode:
    Case GpmcFCLKDivider = 0:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if (ClkActivationTime and ADVWrOffTime are odd) or (ClkActivationTime and ADVWrOffTime are even)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 3)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 3)
    G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    G = 0.5 × ADVExtraDelay × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime) is a multiple of 4)
    G = (1 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 1) is a multiple of 4)
    G = (2 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 2) is a multiple of 4)
    G = (3 + 0.5 × ADVExtraDelay) × GPMC_FCLK if ((ADVWrOffTime – ClkActivationTime – 3) is a multiple of 4)
  8. For OE falling edge (OE activated):
    Case GpmcFCLKDivider = 0:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOnTime are odd) or (ClkActivationTime and OEOnTime are even)
    - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime – ClkActivationTime) is a multiple of 3)
    - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 1) is a multiple of 3)
    - H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOnTime - ClkActivationTime) is a multiple of 4)
    - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 1) is a multiple of 4)
    - H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 2) is a multiple of 4)
    - H = (3 + 0.5 × OEExtraDelay)) × GPMC_FCLK if ((OEOnTime - ClkActivationTime - 3) is a multiple of 4)
    For OE rising edge (OE deactivated):
    Case GpmcFCLKDivider = 0:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK if (ClkActivationTime and OEOffTime are odd) or (ClkActivationTime and OEOffTime are even)
    - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 3)
    - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 3)
    - H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - H = 0.5 × OEExtraDelay × GPMC_FCLK if ((OEOffTime – ClkActivationTime) is a multiple of 4)
    - H = (1 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 1) is a multiple of 4)
    - H = (2 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 2) is a multiple of 4)
    - H = (3 + 0.5 × OEExtraDelay) × GPMC_FCLK if ((OEOffTime – ClkActivationTime – 3) is a multiple of 4)
  9. For WE falling edge (WE activated):
    Case GpmcFCLKDivider = 0:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOnTime are odd) or (ClkActivationTime and WEOnTime are even)
    - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime – ClkActivationTime) is a multiple of 3)
    - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 1) is a multiple of 3)
    - I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOnTime - ClkActivationTime) is a multiple of 4)
    - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 1) is a multiple of 4)
    - I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 2) is a multiple of 4)
    - I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOnTime - ClkActivationTime - 3) is a multiple of 4)
    For WE rising edge (WE deactivated):
    Case GpmcFCLKDivider = 0:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK
    Case GpmcFCLKDivider = 1:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK if (ClkActivationTime and WEOffTime are odd) or (ClkActivationTime and WEOffTime are even)
    - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK otherwise
    Case GpmcFCLKDivider = 2:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime – ClkActivationTime) is a multiple of 3)
    - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 1) is a multiple of 3)
    - I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime – ClkActivationTime – 2) is a multiple of 3)
    Case GpmcFCLKDivider = 3:
    - I = 0.5 × WEExtraDelay × GPMC_FCLK if ((WEOffTime - ClkActivationTime) is a multiple of 4)
    - I = (1 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 1) is a multiple of 4)
    - I = (2 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 2) is a multiple of 4)
    - I = (3 + 0.5 × WEExtraDelay) × GPMC_FCLK if ((WEOffTime - ClkActivationTime - 3) is a multiple of 4)
  10. J = GPMC_FCLK period, where GPMC_FCLK is the General Purpose Memory Controller internal functional clock
  11. For read:
    K = (ADVRdOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
    For write: K = (ADVWrOffTime – ADVOnTime) × (TimeParaGranularity + 1) × GPMC_FCLK
  12. The gpmc_clk output clock maximum and minimum frequency is programmable in the I/F module by setting the GPMC_CONFIG1_CSx configuration register bit fields GpmcFCLKDivider
  13. gpio6_16 programmed to MUXMODE=9 (clkout1), CM_CLKSEL_CLKOUTMUX1 programmed to 7 (CORE_DPLL_OUT_DCLK), CM_CLKSEL_CORE_DPLL_OUT_CLK_CLKOUTMUX programmed to 1.
  14. CSEXTRADELAY = 0, ADVEXTRADELAY = 0, WEEXTRADELAY = 0, OEEXTRADELAY = 0. Extra half-GPMC_FCLK cycle delay mode is not timed.
TDA2P-ACD vayu_gpmc_01.gifFigure 5-23 GPMC / Multiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)

  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
TDA2P-ACD vayu_gpmc_02.gifFigure 5-24 GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Single Read -
(GpmcFCLKDivider = 0)(1)(2)

  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
TDA2P-ACD vayu_gpmc_03.gifFigure 5-25 GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
  1. In gpmc_csi, i= 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
TDA2P-ACD vayu_gpmc_04.gifFigure 5-26 GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Read 4x16 bits -
(GpmcFCLKDivider = 0)(1)(2)
  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
TDA2P-ACD vayu_gpmc_05.gifFigure 5-27 GPMC / Multiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits -
(GpmcFCLKDivider = 0)(1)(2)
  1. In gpmc_csi, i = 0 to 7.
  2. In gpmc_waitj, j = 0 to 1.
TDA2P-ACD vayu_gpmc_06.gifFigure 5-28 GPMC / Nonmultiplexed 16bits NOR Flash - Synchronous Burst Write 4x16bits - (GpmcFCLKDivider = 0)(1)(2)
  1. In gpmc_csi, i = 1 to 7.
  2. In gpmc_waitj, j = 0 to 1.
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