ZHCSJ49F March   2017  – February 2019 TDA2P-ACD

PRODUCTION DATA.  

  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Device Comparison Table
    2. 3.2 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. 4.3.1  VIP
      2. 4.3.2  DSS
      3. 4.3.3  HDMI
      4. 4.3.4  Camera Serial Interface 2 CAL bridge (CSI2)
      5. 4.3.5  EMIF
      6. 4.3.6  GPMC
      7. 4.3.7  Timers
      8. 4.3.8  I2C
      9. 4.3.9  UART
      10. 4.3.10 McSPI
      11. 4.3.11 QSPI
      12. 4.3.12 McASP
      13. 4.3.13 USB
      14. 4.3.14 SATA
      15. 4.3.15 PCIe
      16. 4.3.16 DCAN and MCAN
      17. 4.3.17 GMAC_SW
      18. 4.3.18 eMMC/SD/SDIO
      19. 4.3.19 GPIO
      20. 4.3.20 PWM
      21. 4.3.21 System and Miscellaneous
        1. 4.3.21.1 Sysboot Interface
        2. 4.3.21.2 PRCM
        3. 4.3.21.3 SDMA
        4. 4.3.21.4 INTC
        5. 4.3.21.5 Observability
        6. 4.3.21.6 Power Supplies
      22. 4.3.22 Test Interfaces
    4. 4.4 Pin Multiplexing
    5. 4.5 Connections for Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Power-On Hours (POH) Limits
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Operating Performance Points
      1. 5.5.1 AVS and ABB Requirements
      2. 5.5.2 Voltage And Core Clock Specifications
      3. 5.5.3 Maximum Supported Frequency
    6. 5.6  Power Consumption Summary
    7. 5.7  Electrical Characteristics
      1. Table 5-6  LVCMOS DDR DC Electrical Characteristics
      2. Table 5-7  Dual Voltage LVCMOS I2C DC Electrical Characteristics
      3. Table 5-8  IQ1833 Buffers DC Electrical Characteristics
      4. Table 5-9  LVCMOS CSI2 DC Electrical Characteristics
      5. Table 5-10 IHHV1833 Buffers DC Electrical Characteristics
      6. Table 5-11 Dual Voltage SDIO1833 DC Electrical Characteristics
      7. Table 5-12 Dual Voltage LVCMOS DC Electrical Characteristics
      8. 5.7.1      HDMIPHY DC Electrical Characteristics
      9. 5.7.2      SATAPHY DC Electrical Characteristics
      10. 5.7.3      USBPHY DC Electrical Characteristics
      11. 5.7.4      PCIEPHY DC Electrical Characteristics
    8. 5.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. Table 5-13 Recommended Operating Conditions for OTP eFuse Programming
      2. 5.8.1      Hardware Requirements
      3. 5.8.2      Programming Sequence
      4. 5.8.3      Impact to Your Hardware Warranty
    9. 5.9  Thermal Resistance Characteristics
      1. 5.9.1 Package Thermal Characteristics
    10. 5.10 Timing Requirements and Switching Characteristics
      1. 5.10.1 Timing Parameters and Information
        1. 5.10.1.1 Parameter Information
          1. 5.10.1.1.1 1.8V and 3.3V Signal Transition Levels
          2. 5.10.1.1.2 1.8V and 3.3V Signal Transition Rates
          3. 5.10.1.1.3 Timing Parameters and Board Routing Analysis
      2. 5.10.2 Interface Clock Specifications
        1. 5.10.2.1 Interface Clock Terminology
        2. 5.10.2.2 Interface Clock Frequency
      3. 5.10.3 Power Supply Sequences
      4. 5.10.4 Clock Specifications
        1. 5.10.4.1 Input Clocks / Oscillators
          1. 5.10.4.1.1 OSC0 External Crystal
          2. 5.10.4.1.2 OSC0 Input Clock
          3. 5.10.4.1.3 Auxiliary Oscillator OSC1 Input Clock
            1. 5.10.4.1.3.1 OSC1 External Crystal
            2. 5.10.4.1.3.2 OSC1 Input Clock
        2. 5.10.4.2 RC On-die Oscillator Clock
        3. 5.10.4.3 Output Clocks
        4. 5.10.4.4 DPLLs, DLLs
          1. 5.10.4.4.1 DPLL Characteristics
          2. 5.10.4.4.2 DLL Characteristics
          3. 5.10.4.4.3 DPLL and DLL Noise Isolation
      5. 5.10.5 Recommended Clock and Control Signal Transition Behavior
      6. 5.10.6 Peripherals
        1. 5.10.6.1  Timing Test Conditions
        2. 5.10.6.2  Virtual and Manual I/O Timing Modes
        3. 5.10.6.3  VIP
        4. 5.10.6.4  DSS
        5. 5.10.6.5  HDMI
        6. 5.10.6.6  EMIF
        7. 5.10.6.7  GPMC
          1. 5.10.6.7.1 GPMC/NOR Flash Interface Synchronous Timing
          2. 5.10.6.7.2 GPMC/NOR Flash Interface Asynchronous Timing
          3. 5.10.6.7.3 GPMC/NAND Flash Interface Asynchronous Timing
        8. 5.10.6.8  Timers
        9. 5.10.6.9  I2C
          1. Table 5-59 Timing Requirements for I2C Input Timings
          2. Table 5-60 Timing Requirements for I2C HS-Mode (I2C3/4/5 Only)
          3. Table 5-61 Switching Characteristics Over Recommended Operating Conditions for I2C Output Timings
        10. 5.10.6.10 UART
          1. Table 5-62 Timing Requirements for UART
          2. Table 5-63 Switching Characteristics Over Recommended Operating Conditions for UART
        11. 5.10.6.11 McSPI
        12. 5.10.6.12 QSPI
        13. 5.10.6.13 McASP
          1. Table 5-70 Timing Requirements for McASP1
          2. Table 5-71 Timing Requirements for McASP2
          3. Table 5-72 Timing Requirements for McASP3/4/5/6/7/8
          4. Table 5-73 Switching Characteristics Over Recommended Operating Conditions for McASP1
          5. Table 5-74 Switching Characteristics Over Recommended Operating Conditions for McASP2
          6. Table 5-75 Switching Characteristics Over Recommended Operating Conditions for McASP3/4/5/6/7/8
        14. 5.10.6.14 USB
          1. 5.10.6.14.1 USB1 DRD PHY
          2. 5.10.6.14.2 USB2 PHY
          3. 5.10.6.14.3 USB3 and USB4 DRD ULPI—SDR—Slave Mode—12-pin Mode
        15. 5.10.6.15 SATA
        16. 5.10.6.16 PCIe
        17. 5.10.6.17 CAN
          1. 5.10.6.17.1 DCAN
          2. 5.10.6.17.2 MCAN-FD
          3. Table 5-90  Timing Requirements for CANx Receive
          4. Table 5-91  Switching Characteristics Over Recommended Operating Conditions for CANx Transmit
        18. 5.10.6.18 GMAC_SW
          1. 5.10.6.18.1 GMAC MII Timings
            1. Table 5-92 Timing Requirements for miin_rxclk - MII Operation
            2. Table 5-93 Timing Requirements for miin_txclk - MII Operation
            3. Table 5-94 Timing Requirements for GMAC MIIn Receive 10/100 Mbit/s
            4. Table 5-95 Switching Characteristics Over Recommended Operating Conditions for GMAC MIIn Transmit 10/100 Mbits/s
          2. 5.10.6.18.2 GMAC MDIO Interface Timings
          3. 5.10.6.18.3 GMAC RMII Timings
            1. Table 5-100 Timing Requirements for GMAC REF_CLK - RMII Operation
            2. Table 5-101 Timing Requirements for GMAC RMIIn Receive
            3. Table 5-102 Switching Characteristics Over Recommended Operating Conditions for GMAC REF_CLK - RMII Operation
            4. Table 5-103 Switching Characteristics Over Recommended Operating Conditions for GMAC RMIIn Transmit 10/100 Mbits/s
          4. 5.10.6.18.4 GMAC RGMII Timings
            1. Table 5-107 Timing Requirements for rgmiin_rxc - RGMIIn Operation
            2. Table 5-108 Timing Requirements for GMAC RGMIIn Input Receive for 10/100/1000 Mbps
            3. Table 5-109 Switching Characteristics Over Recommended Operating Conditions for rgmiin_txctl - RGMIIn Operation for 10/100/1000 Mbit/s
            4. Table 5-110 Switching Characteristics for GMAC RGMIIn Output Transmit for 10/100/1000 Mbps
        19. 5.10.6.19 eMMC/SD/SDIO
          1. 5.10.6.19.1 MMC1—SD Card Interface
            1. 5.10.6.19.1.1 Default speed, 4-bit data, SDR, half-cycle
            2. 5.10.6.19.1.2 High speed, 4-bit data, SDR, half-cycle
            3. 5.10.6.19.1.3 SDR12, 4-bit data, half-cycle
            4. 5.10.6.19.1.4 SDR25, 4-bit data, half-cycle
            5. 5.10.6.19.1.5 UHS-I SDR50, 4-bit data, half-cycle
            6. 5.10.6.19.1.6 UHS-I SDR104, 4-bit data, half-cycle
            7. 5.10.6.19.1.7 UHS-I DDR50, 4-bit data
          2. 5.10.6.19.2 MMC2 — eMMC
            1. 5.10.6.19.2.1 Standard JC64 SDR, 8-bit data, half cycle
            2. 5.10.6.19.2.2 High-Speed JC64 SDR, 8-bit data, half cycle
            3. 5.10.6.19.2.3 High-speed HS200 JC64 SDR, 8-bit data, half cycle
            4. 5.10.6.19.2.4 High-Speed JC64 DDR, 8-bit data
          3. 5.10.6.19.3 MMC3 and MMC4—SDIO/SD
            1. 5.10.6.19.3.1 MMC3 and MMC4, SD Default Speed
            2. 5.10.6.19.3.2 MMC3 and MMC4, SD High Speed
            3. 5.10.6.19.3.3 MMC3 and MMC4, SD and SDIO SDR12 Mode
            4. 5.10.6.19.3.4 MMC3 and MMC4, SD SDR25 Mode
            5. 5.10.6.19.3.5 MMC3 SDIO High-Speed UHS-I SDR50 Mode, Half Cycle
        20. 5.10.6.20 GPIO
        21. 5.10.6.21 System and Miscellaneous interfaces
      7. 5.10.7 Emulation and Debug Subsystem
        1. 5.10.7.1 JTAG
          1. 5.10.7.1.1 JTAG Electrical Data/Timing
            1. Table 5-159 Timing Requirements for IEEE 1149.1 JTAG
            2. Table 5-160 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
            3. Table 5-161 Timing Requirements for IEEE 1149.1 JTAG With RTCK
            4. Table 5-162 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG With RTCK
        2. 5.10.7.2 Trace Port Interface Unit (TPIU)
          1. 5.10.7.2.1 TPIU PLL DDR Mode
  6. 6Detailed Description
    1. 6.1  Description
    2. 6.2  Functional Block Diagram
    3. 6.3  MPU
    4. 6.4  DSP Subsystem
    5. 6.5  ISS
    6. 6.6  IVA
    7. 6.7  EVE
    8. 6.8  IPU
    9. 6.9  VPE
    10. 6.10 GPU
    11. 6.11 Memory Subsystem
      1. 6.11.1 EMIF
      2. 6.11.2 GPMC
      3. 6.11.3 ELM
      4. 6.11.4 OCMC
    12. 6.12 Interprocessor Communication
      1. 6.12.1 Mailbox
      2. 6.12.2 Spinlock
    13. 6.13 Interrupt Controller
    14. 6.14 EDMA
    15. 6.15 Peripherals
      1. 6.15.1  VIP
      2. 6.15.2  DSS
      3. 6.15.3  Timers
      4. 6.15.4  I2C
      5. 6.15.5  UART
        1. 6.15.5.1 UART Features
        2. 6.15.5.2 IrDA Features
        3. 6.15.5.3 CIR Features
      6. 6.15.6  McSPI
      7. 6.15.7  QSPI
      8. 6.15.8  McASP
      9. 6.15.9  USB
      10. 6.15.10 SATA
      11. 6.15.11 PCIe
      12. 6.15.12 CAN
      13. 6.15.13 GMAC_SW
      14. 6.15.14 CSI2
        1. 6.15.14.1 CSI-2 MIPI D-PHY
      15. 6.15.15 eMMC/SD/SDIO
      16. 6.15.16 GPIO
      17. 6.15.17 ePWM
      18. 6.15.18 eCAP
      19. 6.15.19 eQEP
    16. 6.16 On-Chip Debug
  7. 7Applications, Implementation, and Layout
    1. 7.1 Introduction
      1. 7.1.1 Initial Requirements and Guidelines
    2. 7.2 Power Optimizations
      1. 7.2.1 Step 1: PCB Stack-up
      2. 7.2.2 Step 2: Physical Placement
      3. 7.2.3 Step 3: Static Analysis
        1. 7.2.3.1 PDN Resistance and IR Drop
      4. 7.2.4 Step 4: Frequency Analysis
      5. 7.2.5 System ESD Generic Guidelines
        1. 7.2.5.1 System ESD Generic PCB Guideline
        2. 7.2.5.2 Miscellaneous EMC Guidelines to Mitigate ESD Immunity
      6. 7.2.6 EMI / EMC Issues Prevention
        1. 7.2.6.1 Signal Bandwidth
        2. 7.2.6.2 Signal Routing
          1. 7.2.6.2.1 Signal Routing—Sensitive Signals and Shielding
          2. 7.2.6.2.2 Signal Routing—Outer Layer Routing
        3. 7.2.6.3 Ground Guidelines
          1. 7.2.6.3.1 PCB Outer Layers
          2. 7.2.6.3.2 Metallic Frames
          3. 7.2.6.3.3 Connectors
          4. 7.2.6.3.4 Guard Ring on PCB Edges
          5. 7.2.6.3.5 Analog and Digital Ground
    3. 7.3 Core Power Domains
      1. 7.3.1 General Constraints and Theory
      2. 7.3.2 Voltage Decoupling
      3. 7.3.3 Static PDN Analysis
      4. 7.3.4 Dynamic PDN Analysis
      5. 7.3.5 Power Supply Mapping
      6. 7.3.6 DPLL Voltage Requirement
      7. 7.3.7 Loss of Input Power Event
      8. 7.3.8 Example PCB Design
        1. 7.3.8.1 Example Stack-up
        2. 7.3.8.2 vdd_mpu Example Analysis
    4. 7.4 Single-Ended Interfaces
      1. 7.4.1 General Routing Guidelines
      2. 7.4.2 QSPI Board Design and Layout Guidelines
    5. 7.5 Differential Interfaces
      1. 7.5.1 General Routing Guidelines
      2. 7.5.2 USB 2.0 Board Design and Layout Guidelines
        1. 7.5.2.1 Background
        2. 7.5.2.2 USB PHY Layout Guide
          1. 7.5.2.2.1 General Routing and Placement
          2. 7.5.2.2.2 Specific Guidelines for USB PHY Layout
            1. 7.5.2.2.2.1  Analog, PLL, and Digital Power Supply Filtering
            2. 7.5.2.2.2.2  Analog, Digital, and PLL Partitioning
            3. 7.5.2.2.2.3  Board Stackup
            4. 7.5.2.2.2.4  Cable Connector Socket
            5. 7.5.2.2.2.5  Clock Routings
            6. 7.5.2.2.2.6  Crystals/Oscillator
            7. 7.5.2.2.2.7  DP/DM Trace
            8. 7.5.2.2.2.8  DP/DM Vias
            9. 7.5.2.2.2.9  Image Planes
            10. 7.5.2.2.2.10 JTAG Interface
            11. 7.5.2.2.2.11 Power Regulators
        3. 7.5.2.3 Electrostatic Discharge (ESD)
          1. 7.5.2.3.1 IEC ESD Stressing Test
            1. 7.5.2.3.1.1 Test Mode
            2. 7.5.2.3.1.2 Air Discharge Mode
            3. 7.5.2.3.1.3 Test Type
          2. 7.5.2.3.2 TI Component Level IEC ESD Test
          3. 7.5.2.3.3 Construction of a Custom USB Connector
          4. 7.5.2.3.4 ESD Protection System Design Consideration
        4. 7.5.2.4 References
      3. 7.5.3 USB 3.0 Board Design and Layout Guidelines
        1. 7.5.3.1 USB 3.0 interface introduction
        2. 7.5.3.2 USB 3.0 General routing rules
      4. 7.5.4 HDMI Board Design and Layout Guidelines
        1. 7.5.4.1 HDMI Interface Schematic
        2. 7.5.4.2 TMDS General Routing Guidelines
        3. 7.5.4.3 TPD5S115
        4. 7.5.4.4 HDMI ESD Protection Device (Required)
        5. 7.5.4.5 PCB Stackup Specifications
        6. 7.5.4.6 Grounding
      5. 7.5.5 SATA Board Design and Layout Guidelines
        1. 7.5.5.1 SATA Interface Schematic
        2. 7.5.5.2 Compatible SATA Components and Modes
        3. 7.5.5.3 PCB Stackup Specifications
        4. 7.5.5.4 Routing Specifications
      6. 7.5.6 PCIe Board Design and Layout Guidelines
        1. 7.5.6.1 PCIe Connections and Interface Compliance
          1. 7.5.6.1.1 Coupling Capacitors
          2. 7.5.6.1.2 Polarity Inversion
        2. 7.5.6.2 Non-standard PCIe connections
          1. 7.5.6.2.1 PCB Stackup Specifications
          2. 7.5.6.2.2 Routing Specifications
            1. 7.5.6.2.2.1 Impedance
            2. 7.5.6.2.2.2 Differential Coupling
            3. 7.5.6.2.2.3 Pair Length Matching
        3. 7.5.6.3 LJCB_REFN/P Connections
    6. 7.6 CSI2 Board Design and Routing Guidelines
      1. 7.6.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
        1. 7.6.1.1 General Guidelines
        2. 7.6.1.2 Length Mismatch Guidelines
          1. 7.6.1.2.1 CSI2_0 and CSI2_1 MIPI CSI-2 (1.5 Gbps)
        3. 7.6.1.3 Frequency-domain Specification Guidelines
    7. 7.7 DDR2/DDR3 Board Design and Layout Guidelines
      1. 7.7.1 DDR2/DDR3 General Board Layout Guidelines
      2. 7.7.2 DDR2 Board Design and Layout Guidelines
        1. 7.7.2.1 Board Designs
        2. 7.7.2.2 DDR2 Interface
          1. 7.7.2.2.1  DDR2 Interface Schematic
          2. 7.7.2.2.2  Compatible JEDEC DDR2 Devices
          3. 7.7.2.2.3  PCB Stackup
          4. 7.7.2.2.4  Placement
          5. 7.7.2.2.5  DDR2 Keepout Region
          6. 7.7.2.2.6  Bulk Bypass Capacitors
          7. 7.7.2.2.7  High-Speed Bypass Capacitors
          8. 7.7.2.2.8  Net Classes
          9. 7.7.2.2.9  DDR2 Signal Termination
          10. 7.7.2.2.10 VREF Routing
        3. 7.7.2.3 DDR2 CK and ADDR_CTRL Routing
      3. 7.7.3 DDR3 Board Design and Layout Guidelines
        1. 7.7.3.1  Board Designs
        2. 7.7.3.2  DDR3 EMIF
        3. 7.7.3.3  DDR3 Device Combinations
        4. 7.7.3.4  DDR3 Interface Schematic
          1. 7.7.3.4.1 32-Bit DDR3 Interface
          2. 7.7.3.4.2 16-Bit DDR3 Interface
        5. 7.7.3.5  Compatible JEDEC DDR3 Devices
        6. 7.7.3.6  PCB Stackup
        7. 7.7.3.7  Placement
        8. 7.7.3.8  DDR3 Keepout Region
        9. 7.7.3.9  Bulk Bypass Capacitors
        10. 7.7.3.10 High-Speed Bypass Capacitors
          1. 7.7.3.10.1 Return Current Bypass Capacitors
        11. 7.7.3.11 Net Classes
        12. 7.7.3.12 DDR3 Signal Termination
        13. 7.7.3.13 VREF_DDR Routing
        14. 7.7.3.14 VTT
        15. 7.7.3.15 CK and ADDR_CTRL Topologies and Routing Definition
          1. 7.7.3.15.1 Four DDR3 Devices
            1. 7.7.3.15.1.1 CK and ADDR_CTRL Topologies, Four DDR3 Devices
            2. 7.7.3.15.1.2 CK and ADDR_CTRL Routing, Four DDR3 Devices
          2. 7.7.3.15.2 Two DDR3 Devices
            1. 7.7.3.15.2.1 CK and ADDR_CTRL Topologies, Two DDR3 Devices
            2. 7.7.3.15.2.2 CK and ADDR_CTRL Routing, Two DDR3 Devices
          3. 7.7.3.15.3 One DDR3 Device
            1. 7.7.3.15.3.1 CK and ADDR_CTRL Topologies, One DDR3 Device
            2. 7.7.3.15.3.2 CK and ADDR/CTRL Routing, One DDR3 Device
        16. 7.7.3.16 Data Topologies and Routing Definition
          1. 7.7.3.16.1 DQS and DQ/DM Topologies, Any Number of Allowed DDR3 Devices
          2. 7.7.3.16.2 DQS and DQ/DM Routing, Any Number of Allowed DDR3 Devices
        17. 7.7.3.17 Routing Specification
          1. 7.7.3.17.1 CK and ADDR_CTRL Routing Specification
          2. 7.7.3.17.2 DQS and DQ Routing Specification
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature and Orderable Information
      1. 8.1.1 Standard Package Symbolization
      2. 8.1.2 Device Naming Convention
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
      1. 8.3.1 FCC Warning
      2. 8.3.2 Information About Cautions and Warnings
    4. 8.4 Receiving Notification of Documentation Updates
    5. 8.5 Community Resources
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9Mechanical Packaging Information
    1. 9.1 Mechanical Data

封装选项

请参考 PDF 数据表获取器件具体的封装图。

机械数据 (封装 | 引脚)
  • ACD|784
散热焊盘机械数据 (封装 | 引脚)
订购信息

3.1 Device Comparison Table

Table 3-1 shows a comparison between devices, highlighting the differences.

Table 3-1 Device Comparison(6)

Features Device
TDA2PSxx TDA2PHxx
TDA2PSXx TDA2PHGx TDA2PHFx TDA2PHVx TDA2PHAx
CTRL_WKUP_STD_FUSE_DIE_ID_2[31:24] Base PN register bitfield value(5)(6) 51 (0x33) 42 (0x2A) 41 (0x29) 38 (0x26) 37 (0x25)
Processors/ Accelerators
Speed Grades V V,R, D U V,R, D V,R, D
Arm Dual Cortex-A15 Microprocessor Subsystem MPU core 0 Yes Yes Yes Yes Yes
MPU core 1 Yes No Yes No No
C66x VLIW DSP DSP1 (with L1D ECC) Yes Yes Yes Yes Yes
DSP2 (with L1D ECC) Yes Yes Yes Yes Yes
BitBLT 2D Hardware Acceleration Engine BB2D Yes Yes No No No
Display Subsystem VOUT1 Yes(1) Yes(1) Yes(1) Yes(1) Yes(1)
VOUT2 Yes(1) Yes(1) Yes(1) Yes(1) Yes(1)
VOUT3 Yes(1) Yes(1) Yes(1) Yes(1) Yes(1)
HDMI Yes Yes Yes Yes Yes
Embedded Vision Engine (EVE) EVE1 Yes Yes Yes Yes Yes
EVE2 Yes Yes Yes Yes Yes
Arm Dual Cortex-M4 Image Processing Unit IPU1 Yes Yes Yes Yes Yes
IPU2 Yes Yes Yes Yes Yes
Image Video Accelarator IVA Yes Yes Yes Yes No
SGX544 Dual-Core 3D Graphics Processing Unit GPU Yes Yes No No No
Imaging Subsystem with WDR & LDC (ISS) ISP Yes Yes Yes Yes No
WDR & Mesh LDC(4) Yes Yes Yes Yes No
CAL_B Yes Yes Yes Yes No
Video Input Port (VIP) VIP1 vin1a Yes Yes Yes Yes Yes
vin1b Yes Yes Yes Yes Yes
vin2a Yes Yes Yes Yes Yes
vin2b Yes Yes Yes Yes Yes
VIP2 vin3a Yes Yes Yes Yes Yes
vin3b Yes Yes Yes Yes Yes
vin4a Yes Yes Yes Yes Yes
vin4b Yes Yes Yes Yes Yes
VIP3 vin5a No No No No No
vin6a No No No No No
Video Processing Engine VPE Yes Yes Yes Yes Yes
Camera Adaptation Layer (CAL) Camera Serial Interface 2 (CSI2) CSI2_0
(CLK + 4 Data)		 Yes Yes Yes Yes Yes
CSI2_1
(CLK + 2 Data)		 Yes Yes Yes Yes Yes
Program/Data Storage
On-Chip Shared Memory (RAM) OCMC_RAM1 512 KB 512 KB 512 KB 512 KB 512 KB
OCMC_RAM2 1 MB 1 MB 1 MB 1 MB 1 MB
OCMC_RAM3 1 MB 1 MB 1 MB 1 MB 1 MB
General-Purpose Memory Controller GPMC Yes Yes Yes Yes Yes
DDR2/DDR3/DDR3L Memory Controller(2) EMIF1 (with R-mod-W ECC) up to 2 GB up to 2 GB up to 2 GB up to 2 GB up to 2 GB
EMIF2 up to 2 GB up to 2 GB up to 2 GB up to 2 GB up to 2 GB
Dynamic Memory Manager DMM Yes Yes Yes Yes Yes
Radio Support
Audio Tracking Logic ATL No No No No No
Viterbi Coprocessor VCP1 No No No No No
VCP2 No No No No No
Peripherals
Controller Area Network Interface (CAN) DCAN1(3) Yes Yes Yes Yes Yes
DCAN2(3) Yes Yes Yes Yes Yes
MCAN with FD(3) Yes Yes Yes Yes Yes
Enhanced DMA EDMA Yes Yes Yes Yes Yes
System DMA DMA SYSTEM Yes Yes Yes Yes Yes
Ethernet Subsystem (Ethernet SS) GMAC_SW[0] Yes Yes Yes Yes Yes
GMAC_SW[1] Yes Yes Yes Yes Yes
General-Purpose IO GPIO up to 247 up to 247 up to 247 up to 247 up to 247
Inter-Integrated Circuit Interface I2C 5 5 5 5 5
System Mailbox Module MAILBOX 13 13 13 13 13
Media Local Bus MLB No No No No No
Multi-Channel Audio Serial Port McASP1 16 serializers 16 serializers 16 serializers 16 serializers 16 serializers
McASP2 16 serializers 16 serializers 16 serializers 16 serializers 16 serializers
McASP3 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP4 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP5 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP6 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP7 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
McASP8 4 serializers 4 serializers 4 serializers 4 serializers 4 serializers
MultiMedia Card/Secure Digital/Secure Digital Input Output Interface (MMC/SD/SDIO) MMC1 Yes Yes Yes Yes Yes
MMC2 Yes Yes Yes Yes Yes
MMC3 Yes Yes Yes Yes Yes
MMC4 Yes Yes Yes Yes Yes
PCI Express 3.0 Port with Integrated PHY PCIe_SS1 Yes Yes Yes Yes Yes
PCIe_SS2 Yes Yes Yes Yes Yes
SATA Gen2 Interface SATA Yes Yes Yes Yes Yes
Real-Time Clock RTCSS No No No No No
Programmable Real-Time Unit Subsystem and Industrial Communication Subsystem PRU-ICSS No No No No No
Multichannel Serial Peripheral Interface McSPI 4 4 4 4 4
HDQ1W HDQ1W No No No No No
Quad SPI QSPI Yes Yes Yes Yes Yes
Spinlock Module SPINLOCK Yes Yes Yes Yes Yes
Keyboard Controller KBD No No No No No
Timers, General-Purpose TIMER 16 16 16 16 16
Timer, Watchdog WATCHDOG TIMER Yes Yes Yes Yes Yes
Pulse-Width Modulation Subsystem PWMSS1 Yes Yes Yes Yes Yes
PWMSS2 Yes Yes Yes Yes Yes
PWMSS3 Yes Yes Yes Yes Yes
Universal Asynchronous Receiver/Transmitter UART 10 10 10 10 10
Universal Serial Bus (USB3.0) USB1 (SuperSpeed, Dual-Role-Device [DRD]) Yes Yes Yes Yes Yes
Universal Serial Bus (USB2.0) USB2 (HighSpeed, Dual-Role-Device [DRD], with embedded HS PHY) Yes Yes Yes Yes Yes
USB3 (HighSpeed, OTG2.0, with ULPI) Yes Yes Yes Yes Yes
USB4 (HighSpeed, OTG2.0, with ULPI) Yes Yes Yes Yes Yes
  1. DSS clock jitter can be improved by providing an external clock source (via inputs vin1a_clk, vin1b_clk) or from internal SATA or PCIe PLLs.
  2. In the Unified L3 memory map, there is maximum of 2 GB of SDRAM space which is available to all L3 initiators including MPU (MPU, GPU, DSP, IVA, DMA, etc). Typically this space is interleaved across both EMIFs to optimize memory performance. If a system populates > 2 GB of physical memory, that additional addressable space can be accessed only by the MPU via the Arm V7 Large Physical Address Extensions (LPAE).
  3. DCAN1 has one pin mux option that can optionally be used for MCAN functionality. DCAN2 has two pin mux options, one of which can be optionally used for MCAN functionality.
  4. Wide Dynamic Range and Lens Distortion Correction.
  5. For more details about the CTRL_WKUP_STD_FUSE_DIE_ID_2 register and Base PN bitfield, see the TDA2Px Technical Reference Manual.
  6. X577Px is the base part number for the superset device. Software should constrain the features used to match the intended production device. The Base PN register bitfield value is 0x69.
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