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ZHCSH24G June 2016 – March 2019 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

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7.13 Multichannel Serial Peripheral Interface (McSPI)

The McSPI is a master/slave synchronous serial bus. There are four separate McSPI modules (SPI1, SPI2, SPI3, and SPI4) in the device. All these four modules support up to four external devices (four chip selects) and are able to work as both master and slave.

The McSPI modules include the following main features:

Serial clock with programmable frequency, polarity, and phase for each channel
Wide selection of SPI word lengths, ranging from 4 to 32 bits
Up to four master channels, or single channel in slave mode
Master multichannel mode:
- Full duplex/half duplex
- Transmit-only/receive-only/transmit-and-receive modes
- Flexible input/output (I/O) port controls per channel
- Programmable clock granularity
- SPI configuration per channel. This means, clock definition, polarity enabling and word width
Power management through wake-up capabilities
Programmable timing control between chip select and external clock generation
Built-in FIFO available for a single channel.
Each SPI module supports multiple chip select pins spim_cs[i], where i = 1 to 4.

NOTE

For more information, see the Serial Communication Interface section of the device TRM.

NOTE

The McSPIm module (m = 1 to 4) is also referred to as SPIm.

Table 7-20, Figure 7-26 and Figure 7-27 present Timing Requirements for McSPI - Master Mode.

Table 7-20 Timing Requirements for SPI - Master Mode

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
SM1	t_c(SPICLK)	Cycle time, spi_sclk ^{⁽¹⁾⁽²⁾}	SPI1/2/3/4	20.8		ns
SM2	t_w(SPICLKL)	Typical Pulse duration, spi_sclk low ^⁽¹⁾		0.5×P-1 ⁽³⁾		ns
SM3	t_w(SPICLKH)	Typical Pulse duration, spi_sclk high ^⁽¹⁾		0.5×P-1 ⁽³⁾		ns
SM4	t_{su(MISO-SPICLK)}	Setup time, spi_d[x] valid before spi_sclk active edge ^⁽¹⁾		2.29		ns
SM5	t_{h(SPICLK-MISO)}	Hold time, spi_d[x] valid after spi_sclk active edge ^⁽¹⁾		2.67		ns
SM6	t_{d(SPICLK-SIMO)}	Delay time, spi_sclk active edge to spi_d[x] transition ^⁽¹⁾	SPI1/2/4	-3.57	3.57	ns
SM6	t_{d(SPICLK-SIMO)}		SPI3	-3.57	3.57	ns
SM7	t_d(CS-SIMO)	Delay time, spi_cs[x] active edge to spi_d[x] transition			3.57	ns
SM8	t_d(CS-SPICLK)	Delay time, spi_cs[x] active to spi_sclk first edge ^⁽¹⁾	MASTER_PHA0 ^⁽⁴⁾	B-4.2 ⁽⁵⁾		ns
SM8	t_d(CS-SPICLK)	Delay time, spi_cs[x] active to spi_sclk first edge ^⁽¹⁾	MASTER_PHA1 ^⁽⁴⁾	A-4.2 ⁽⁶⁾		ns
SM9	t_d(SPICLK-CS)	Delay time, spi_sclk last edge to spi_cs[x] inactive ^⁽¹⁾	MASTER_PHA0 ^⁽⁴⁾	A-4.2 ⁽⁶⁾		ns
SM9	t_d(SPICLK-CS)	Delay time, spi_sclk last edge to spi_cs[x] inactive ^⁽¹⁾	MASTER_PHA1 ^⁽⁴⁾	B-4.2 ⁽⁵⁾		ns

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
Related to the SPI_CLK maximum frequency.
P = SPICLK period.
SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
B = (TCS + 0.5) × TSPICLKREF × Fratio, where TCS is a bit field of the SPI_CH(i)CONF register and Fratio = Even ≥2.
When P = 20.8 ns, A = (TCS + 1) × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register. When P > 20.8 ns, A = (TCS + 0.5) × Fratio × TSPICLKREF, where TCS is a bit field of the SPI_CH(i)CONF register.
The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_McSPI_01.gif

Figure 7-26 McSPI - Master Mode Transmit

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_McSPI_02.gif

Figure 7-27 McSPI - Master Mode Receive

Table 7-21, Figure 7-28 and Figure 7-29 present Timing Requirements for McSPI - Slave Mode.

Table 7-21 Timing Requirements for SPI - Slave Mode^⁽⁵⁾

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
SS1 ^{⁽¹⁾⁽²⁾}	t_c(SPICLK)	Cycle time, spi_sclk	SPI1	25		ns
SS1 ^{⁽¹⁾⁽²⁾}	t_c(SPICLK)	Cycle time, spi_sclk	SPI2/3/4	33.3		ns
SS2 ^⁽¹⁾	t_w(SPICLKL)^⁽³⁾	Typical Pulse duration, spi_sclk low		0.45×P		ns
SS3 ^⁽¹⁾	t_w(SPICLKH)^⁽³⁾	Typical Pulse duration, spi_sclk high		0.45×P		ns
SS4 ^⁽¹⁾	t_{su(SIMO-SPICLK)}	Setup time, spi_d[x] valid before spi_sclk active edge		2.82		ns
SS5 ^⁽¹⁾	t_{h(SPICLK-SIMO)}	Hold time, spi_d[x] valid after spi_sclk active edge		2.82		ns
SS6 ^⁽¹⁾	t_{d(SPICLK-SOMI)}	Delay time, spi_sclk active edge to mcspi_somi transition	SPI1	2	9.8	ns
SS6 ^⁽¹⁾	t_{d(SPICLK-SOMI)}	Delay time, spi_sclk active edge to mcspi_somi transition	SPI2/3/4	2	21	ns
SS7 ^⁽⁴⁾	t_d(CS-SOMI)	Delay time, spi_cs[x] active edge to mcspi_somi transition			16	ns
SS8 ^⁽¹⁾	t_{su(CS-SPICLK)}	Setup time, spi_cs[x] valid before spi_sclk first edge		2.82		ns
SS9 ^⁽¹⁾	t_h(SPICLK-CS)	Hold time, spi_cs[x] valid after spi_sclk last edge		2.82		ns

This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture input data.
When operating the SPI interface in RX-only mode, the minimum Cycle time is 26ns (38.4MHz)
P = SPICLK period.
PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
The IO timings provided in this section are applicable for all combinations of signals for spi1 and spi2. However, the timings are only valid for spi3 and spi4 if signals within a single IOSET are used. The IOSETs are defined in the following tables.

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_McSPI_03.gif

Figure 7-28 McSPI - Slave Mode Transmit

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_McSPI_04.gif

Figure 7-29 McSPI - Slave Mode Receive

CAUTION

The IO timings provided in this section are applicable for all combinations of signals for SPI2 and SPI4. However, the timings are only valid for SPI1 and SPI3 if signals within a single IOSET are used. The IOSETs are defined in Table 7-22.

In Table 7-22 are presented the specific groupings of signals (IOSET) for use with McSPI.

Table 7-22 McSPI1/3 IOSETs

SIGNALS	IOSET1		IOSET2		IOSET3
SIGNALS	BALL	MUX	BALL	MUX	BALL	MUX
SPI1
spi1_sclk	M2	0	M2	0	M2	0
spi1_d1	U6	0	U6	0	U6	0
spi1_d0	T5	0	T5	0	T5	0
spi1_cs0	R6	0	R6	0	R6	0
spi1_cs1					R5	0
spi1_cs2			F14	5
spi1_cs3			C14	5
SPI3
spi3_sclk	F15	4	C6	4
spi3_d1	D14	4	F7	4
spi3_d0	D15	4	E7	4
spi3_cs0	F16	4	B6	4