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ZHCSH24G June 2016 – March 2019 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

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8.9.2.15.1 CK and ADDR_CTRL Routing Specification

Skew within the CK and ADDR_CTRL net classes directly reduces setup and hold margin and, thus, this skew must be controlled. The only way to practically match lengths on a PCB is to lengthen the shorter traces up to the length of the longest net in the net class and its associated clock. A metric to establish this maximum length is Manhattan distance. The Manhattan distance between two points on a PCB is the length between the points when connecting them only with horizontal or vertical segments. A reasonable trace route length is to within a percentage of its Manhattan distance. CACLM is defined as Clock Address Control Longest Manhattan distance.

Given the clock and address pin locations on the processor and the DDR3 memories, the maximum possible Manhattan distance can be determined given the placement. Figure 8-69 and Figure 8-70 show this distance for three loads and two loads, respectively. It is from this distance that the specifications on the lengths of the transmission lines for the address bus are determined. CACLM is determined similarly for other address bus configurations; that is, it is based on the longest net of the CK/ADDR_CTRL net class. For CK and ADDR_CTRL routing, these specifications are contained in Table 8-44.

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_PCB_DDR3_26.gif

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-69 CACLM for Three Address Loads on One Side of PCB

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA SPRS91v_PCB_DDR3_27.gif

A. It is very likely that the longest CK/ADDR_CTRL Manhattan distance will be for Address Input 8 (A8) on the DDR3 memories. CACLM is based on the longest Manhattan distance due to the device placement. Verify the net class that satisfies this criteria and use as the baseline for CK/ADDR_CTRL skew matching and length control.

The length of shorter CK/ADDR_CTRL stubs as well as the length of the terminator stub are not included in this length calculation. Non-included lengths are grayed out in the figure.

Assuming A8 is the longest, CALM = CACLMY + CACLMX + 300 mils.
The extra 300 mils allows for routing down lower than the DDR3 memories and returning up to reach A8.

Figure 8-70 CACLM for Two Address Loads on One Side of PCB

Table 8-44 CK and ADDR_CTRL Routing Specification^{⁽²⁾⁽³⁾}

NO.	PARAMETER	MIN	TYP	MAX	UNIT
CARS31	A1+A2 length			500^⁽¹⁾	ps
CARS32	A1+A2 skew			29	ps
CARS33	A3 length			125	ps
CARS34	A3 skew^⁽⁴⁾			6	ps
CARS35	A3 skew^⁽⁵⁾			6	ps
CARS36	A4 length			125	ps
CARS37	A4 skew			6	ps
CARS38	AS length		5	17^⁽¹⁾	ps
CARS39	AS skew		1.3	14^⁽¹⁾	ps
CARS310	AS+/AS- length		5	12	ps
CARS311	AS+/AS- skew			1	ps
CARS312	AT length^⁽⁶⁾		75		ps
CARS313	AT skew^⁽⁷⁾		14		ps
CARS314	AT skew^⁽⁸⁾			1	ps
CARS315	CK/ADDR_CTRL trace length			1020	ps
CARS316	Vias per trace			3^⁽¹⁾	vias
CARS317	Via count difference			1^⁽¹⁵⁾	vias
CARS318	Center-to-center CK to other DDR3 trace spacing^⁽⁹⁾	4w
CARS319	Center-to-center ADDR_CTRL to other DDR3 trace spacing^{⁽⁹⁾⁽¹⁰⁾}	4w
CARS320	Center-to-center ADDR_CTRL to other ADDR_CTRL trace spacing^⁽⁹⁾	3w
CARS321	CK center-to-center spacing^{⁽¹¹⁾⁽¹²⁾}
CARS322	CK spacing to other net^⁽⁹⁾	4w
CARS323	Rcp^⁽¹³⁾	Zo-1	Zo	Zo+1	Ω
CARS324	Rtt^{⁽¹³⁾⁽¹⁴⁾}	Zo-5	Zo	Zo+5	Ω

Max value is based upon conservative signal integrity approach. This value could be extended only if detailed signal integrity analysis of rise time and fall time confirms desired operation.
The use of vias should be minimized.
Additional bypass capacitors are required when using the DDR_1V5 plane as the reference plane to allow the return current to jump between the DDR_1V5 plane and the ground plane when the net class switches layers at a via.
Non-mirrored configuration (all DDR3 memories on same side of PCB).
Mirrored configuration (one DDR3 device on top of the board and one DDR3 device on the bottom).
While this length can be increased for convenience, its length should be minimized.
ADDR_CTRL net class only (not CK net class). Minimizing this skew is recommended, but not required.
CK net class only.
Center-to-center spacing is allowed to fall to minimum (2w) for up to 1250 mils of routed length.
The ADDR_CTRL net class of the other DDR EMIF is considered other DDR3 trace spacing.
CK spacing set to ensure proper differential impedance.
The most important thing to do is control the impedance so inadvertent impedance mismatches are not created. Generally speaking, center-to-center spacing should be either 2w or slightly larger than 2w to achieve a differential impedance equal to twice the singleended impedance, Zo.
Source termination (series resistor at driver) is specifically not allowed.
Termination values should be uniform across the net class.
Via count difference may increase by 1 only if accurate 3-D modeling of the signal flight times – including accurately modeled signal propagation through vias – has been applied to ensure all segment skew maximums are not exceeded.

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