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ZHCSH24G June 2016 – March 2019 TDA3LA , TDA3LX , TDA3MA , TDA3MD , TDA3MV

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8.7.4.1 DQS[x] and DQ[x] Routing Specification

DQS[x] lines are point-to-point differential and DQ[x] lines are point-to-point single ended. Figure 8-27 and Figure 8-28 represent the supported topologies. Figure 8-29 and Figure 8-30 show the DQS[x] and DQ[x] routing. Figure 8-31 shows the DQLM for the LPDDR2 interface.

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA sprs917_lpddr2_06.gif

x = 0, 1, 2, 3

Figure 8-27 DQS[x] Topology

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA sprs917_lpddr2_07.gif

x = 0, 1, 2, 3

Figure 8-28 DQ[x] Topology

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA sprs917_lpddr2_08.gif

x = 0, 1, 2, 3

Figure 8-29 DQS[x] Routing

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA sprs917_lpddr2_09.gif

x = 0, 1, 2, 3

Figure 8-30 DQ[x] Routing

TDA3MV TDA3MA TDA3MD TDA3LX TDA3LA sprs917_lpddr2_10.gif

There are four DQLMs, one for each data byte, in a 32-bit interface and two DQLMs, one for each data byte, in a 16-bit interface. Each DQLM is the longest Manhattan distance of the byte.

Figure 8-31 DQLM for LPDDR2 Interface

Trace routing specifications for the DQ[x] and the DQS[x] are specified in Table 8-20.

Table 8-20 DQS[x] and DQ[x] Routing Specification⁽¹⁾⁽²⁾

NO.	PARAMETER	MIN	MAX	UNIT
1	DQ0 nominal length⁽³⁾⁽⁴⁾		DQLM0	mils
2	DQ1 nominal length⁽³⁾⁽⁵⁾		DQLM1	mils
3	DQ2 nominal length ⁽³⁾⁽⁶⁾		DQLM2	mils
4	DQ3 nominal length ⁽³⁾⁽⁷⁾		DQLM3	mils
5	DQ[x] skew⁽⁸⁾		10	ps
6	DQS[x] skew		5	ps
7	Via count per each trace in DQ[x], DQS[x]		2
8	Via count difference across a given DQ[x], DQS[x]		0
9	DQS[x]-to-DQ[x] skew⁽⁸⁾⁽⁹⁾		10	ps
10	Center-to-center DQ[x] to other LPDDR2 trace spacing⁽¹⁰⁾⁽¹¹⁾	4		w
11	Center-to-center DQ[x] to other DQ[x] trace spacing⁽¹⁰⁾⁽¹²⁾	3		w
12	DQS[x] center-to-center spacing⁽¹³⁾
13	DQS[x] center-to-center spacing to other net⁽¹⁰⁾	4		w

DQS[x] represents the DQS0, DQS1, DQS2, DQS3 clock net classes, and DQ[x] represents the DQ0, DQ1, DQ2, DQ3 signal net classes.
External termination disallowed. Data termination should use built-in ODT functionality.
DQLMn is the longest Manhattan distance of a byte.
DQLM0 is the longest Manhattan length for the DQ0 net class.
DQLM1 is the longest Manhattan length for the DQ1 net class.
DQLM2 is the longest Manhattan length for the DQ2 net class.
DQLM3 is the longest Manhattan length for the DQ3 net class.
Length matching is only done within a byte. Length matching across bytes is not required.
Each DQS clock net class is length matched to its associated DQ signal net class.
Center-to-center spacing is allowed to fall to minimum for up to 1000 mils of routed length.
Other LPDDR2 trace spacing means signals that are not part of the same DQ[x] signal net class.
This applies to spacing within same DQ[x] signal net class.
DQS[x] pair spacing is set to ensure proper differential impedance. Differential impedance should be Zo x 2, where Zo is the single-ended impedance.

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8.7.4.1 DQS[x] and DQ[x] Routing Specification

Table 8-20 DQS[x] and DQ[x] Routing Specification(1)(2)

Table 8-20 DQS[x] and DQ[x] Routing Specification⁽¹⁾⁽²⁾