7.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

SUPPLY NAME	DESCRIPTION		MIN⁽¹⁾	NOM	MAX⁽¹⁾	UNIT
VDD_CORE	Boot/Active voltage for MAIN domain core supply		0.76⁽¹⁾	0.8	0.84⁽¹⁾	V
VDD_MCU	Boot/Active voltage for MCUSS core supply		0.76⁽¹⁾	0.8	0.89⁽¹⁾	V
VDD_CPU	Boot voltage for CPU core supply, applied at cold power up event		0.76⁽¹⁾	0.8	0.84⁽¹⁾	V
VDD_CPU	Active voltage for CPU core supply, after AVS mode enabled in software		AVS⁽³⁾–5%⁽¹⁾	AVS⁽³⁾	AVS⁽³⁾+5%⁽¹⁾	V
VDD_CPU AVS Range	AVS valid voltage range for VDD_CPU		0.6		0.9	V
VDDAR_*⁽⁷⁾	RAM supplis		0.81	0.85	0.89	V
VDDA_0P8_*⁽⁷⁾	Analog supplies for 0.8V domains		0.76	0.8	0.84	V
VDDA_1P8_*⁽⁷⁾	Analog supplies for 1.8V PHY domains		1.71	1.8	1.89	V
VDDA_3P3_USB⁽⁷⁾	Analog supply for 3.3V USB domain		3.14	3.3	3.46	V
VDDA_*⁽⁷⁾	Analog supply for 1.8V PLL and other domains		1.71	1.8	1.89	V
VDDA_*	Peak to Peak Noise for all VDDA inputs				25	mV
VDDS_DDR_*⁽⁷⁾	DDR inteface power supply		1.06	1.1	1.15	V
VDDS_MMC0	MMC0 IO supply		1.71	1.8	1.89	V
VDDSHV*⁽⁷⁾	Dual Voltage LVCMOS IO supplies	1.8-V operation	1.71	1.8	1.89	V
VDDSHV*⁽⁷⁾	Dual Voltage LVCMOS IO supplies	3.3-V operation	3.14	3.3	3.46	V
USB0_VBUS	Voltage range for USB VBUS comparator input		0	See ⁽⁴⁾	3.46	V
USB0_ID	Voltage range for the USB ID input			See ⁽²⁾		V
VSS	Ground			0		V
T_J	Operating junction temperature range	Automotive	–40		125	°C
		Extended	-40		105	°C
		Commercial	0		90	°C

(1) For all VDD* supply inputs, the voltage at the device ball must never be below the MIN voltage or above the MAX voltage for any amount of time. This requirement includes dynamic voltage events such as AC ripple, voltage transients, voltage dips, and so forth. This is required for all supply inputs, but special care should be given to the VDD_CORE, VDD_MCU, and VDD_CPU domains which have higher transient current demand compared to other rails.

(2) This terminal is connected to analog circuits in the respective USB PHY. The circuit sources a known current while measuring the voltage to determine if the terminal is connected to VSS with a resistance less than 10 Ω or greater than 100 kΩ. The terminal should be connected to ground for USB host operation or open-circuit for USB peripheral operation, and should never be connected to any external voltage source.

(3) The AVS Voltages are device-dependent, voltage domain-dependent, and OPP-dependent. They must be read from the VTM_DEVINFO_VDn. For information about VTM_DEVINFO_VDn Registers address, please refer to Voltage and Thermal Manager section in the device TRM. The power supply should be adjustable over the ranges shown in the VDD_CPU AVS Range entry.

(4) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see USB VBUS Design Guidelines.

(7) VDD_* includes: VDD_CORE, VDD_CPU, VDD_MCU, VDD_MCU_WAKE1, VDD_WAKE0
VDDAR_* includes: VDDAR_CORE, VDDAR_CPU, VDDAR_MCU
VDDA_0P8_* includes: VDDA_0P8_CSIRX0_1, VDDA_0P8_CSIRX2, VDDA_0P8_DLL_MMC0, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C, VDDA_0P8_PLL_DDR0, VDDA_0P8_PLL_DDR1, VDDA_0P8_PLL_DDR2, VDDA_0P8_PLL_DDR3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2, VDDA_0P8_SERDES_C4, VDDA_0P8_SERDES0_1, VDDA_0P8_SERDES2, VDDA_0P8_SERDES4, VDDA_0P8_UFS, VDDA_0P8_USB
VDDA_1P8_* includes: VDDA_1P8_CSIRX0_1, VDDA_1P8_CSIRX2, VDDA_1P8_DSITX, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2, VDDA_1P8_SERDES2_4, VDDA_1P8_SERDES4, VDDA_1P8_UFS, VDDA_1P8_USB
VDDA_* includes: VDDA_ADC0, VDDA_ADC1, VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP10, VDDA_PLLGRP12, VDDA_PLLGRP13, VDDA_PLLGRP2, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_PLLGRP7, VDDA_PLLGRP8, VDDA_PLLGRP9, VDDA_POR_WKUP, VDDA_TEMP0, VDDA_TEMP1, VDDA_TEMP2, VDDA_TEMP3, VDDA_TEMP4, VDDA_WKUP
VDDS_DDR_* includes: VDDS_DDR, VDDS_DDR_C0, VDDS_DDR_C1, VDDS_DDR_C2, VDDS_DDR_C3
VDDSHV* includes: VDDSHV0, VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2, VDDSHV2_MCU, VDDSHV5