米6体育平台手机版

ZHCSKP3K September 2021 – April 2024 TDA4VM , TDA4VM-Q1

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

Tables and figures provided in this section define timing requirements and switching characteristics for clock signals.

Table 6-27 Clock Timng Requiements see Figure 6-20

NO.			MIN	MAX	UNIT
CLK1	t_{c(EXT_REFCLK1)}	Cycle time minimum, EXT_REFCLK1	10		ns
CLK2	t_{w(EXT_REFCLK1H)}	Pulse Duration minimum, EXT_REFCLK1 high	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns
CLK3	t_{w(EXT_REFCLK1L)}	Pulse Duration minimum, EXT_REFCLK1 low	E*0.45⁽¹⁾	E*0.55⁽¹⁾	ns

(1) E = EXT_REFCLK1 cycle time.

Figure 6-20 Clock Timing Requirements

Table 6-28 Clock Switching Characteristics see Figure 6-21

NO.	PARAMETER		MIN	MAX	UNIT
CLK4	t_{c(SYSCLKOUT0)}	Cycle time minimum,SYSCLKOUT0	8		ns
CLK5	t_{w(SYSCLKOUT0H)}	Pulse Duration minimum, SYSCLKOUT0 high	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK6	t_{w(SYSCLKOUT0L)}	Pulse Duration minimum, SYSCLKOUT0 low	A*0.4⁽¹⁾	A*0.6⁽¹⁾	ns
CLK7	t_c(OBSCLK0)	Cycle time minimum, OBSCLK0	5		ns
CLK8	t_w(OBSCLK0H)	Pulse Duration minimum, OBSCLK0 high	B*0.4⁽²⁾	B*0.6⁽²⁾	ns
CLK9	t_w(OBSCLK0L)	Pulse Duration minimum,OBSCLK0 low	B*0.4⁽²⁾	B*0.6⁽²⁾	ns
CLK10	t_c(CLKOUT0)	Cycle time minimum, CLKOUT0	20		ns
CLK11	t_w(CLKOUT0H)	Pulse Duration minimum, CLKOUT0 high	C*0.4⁽³⁾	C*0.6⁽³⁾	ns
CLK12	t_w(CLKOUT0L)	Pulse Duration minimum,CLKOUT0 low	C*0.4⁽³⁾	C*0.6⁽³⁾	ns

(1) A = SYSCLKOUT0 cycle time.

(2) B = OBSCLK0 cycle time.

(3) C = CLKOUT0 cycle time.

Figure 6-21 Clock Switching Characteristics