米6体育平台手机版

ZHCSKP3K September 2021 – April 2024 TDA4VM , TDA4VM-Q1

PRODUCTION DATA

请参考 PDF 数据表获取器件具体的封装图。

6.9.5.21.1.2.4 OSPI Switching Characteristics – DDR Mode

NO.	PARAMETER	DESCRIPTION	MODE	MIN	MAX	UNIT
O1	t_c(CLK)	Cycle time, CLK	1.8V	19		ns
O1	t_c(CLK)	Cycle time, CLK	3.3V	19		ns
O2	t_w(CLKL)	Pulse duration, CLK low		0.475*P - 0.3 ⁽²⁾		ns
O3	t_w(CLKH)	Pulse duration, CLK high		0.475*P - 0.3 ⁽²⁾		ns
O4	t_d(CLK-CSn)	Delay time, CSn active edge to CLK rising edge	1.8V	0.475 * P + 0.975 * N * R ⁽²⁾⁽³⁾⁽⁵⁾	0.475 * P + 0.975 * N * R + 1 ⁽²⁾⁽³⁾⁽⁵⁾	ns
O4	t_d(CLK-CSn)	Delay time, CSn active edge to CLK rising edge	3.3V	0.475 * P + 0.975 * N * R ⁽²⁾⁽³⁾⁽⁵⁾	0.475 * P + 0.975 * N * R + 1⁽²⁾⁽³⁾⁽⁵⁾	ns
O5	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	1.8V	0.475 * P + 0.975 * N * R - 7⁽²⁾⁽⁴⁾⁽⁵⁾	0.475 * P + 0.975 * N * R ⁽²⁾⁽⁴⁾⁽⁵⁾	ns
O5	t_d(CLK-CSn)	Delay time, CLK rising edge to CSn inactive edge	3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX	0.475 * P + 0.975 * N * R - 7⁽²⁾⁽⁴⁾⁽⁵⁾	0.475 * P + 0.975 * N * R ⁽²⁾⁽⁴⁾⁽⁵⁾	ns
O6	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition⁽¹⁾	1.8V, OSPI0 DDR TX; 1.8V, OSPI1 DDR TX	-7.71	-1.56	ns
O6	t_d(CLK-D)	Delay time, CLK active edge to D[i:0] transition⁽¹⁾	3.3V, OSPI0 DDR TX; 3.3V, OSPI1 DDR TX	-7.71	-1.56	ns

(1) i in [i:0] = 7 for OSPI0, i in [i:0] = 3 for OSPI1

(2) P = CLK cycle time = SCLK period

(3) N = OSPI_DEV_DELAY_REG[D_INIT_FLD]

(4) N = OSPI_DEV_DELAY_REG[D_AFTER_FLD]

(5) R = refclk

Figure 6-114 OSPI Switching Characteristics – DDR