7.1 Absolute Maximum Ratings

over operating free–air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

PARAMETER			MIN	MAX	UNIT
VDD_*⁽⁷⁾	Core supplies		–0.3	1.05	V
VDDAR_*⁽⁷⁾	RAM supplies		–0.3	1.05	V
VDDA_0P8_*⁽⁷⁾	Analog supplies for 0.8V domains		–0.3	1.05	V
VDDA_1P8_*⁽⁷⁾	Analog supplies for 1.8 V PHY domains		–0.3	2.2	V
VDDA_3P3_USB	Analog supply for 3.3V USB domain		–0.3	3.8	V
VDDA_*⁽⁷⁾	Analog supply for 1.8V PLL and other domains		–0.3	2.2	V
VDDS_DDR_*⁽⁷⁾	DDR inteface power supplies		–0.3	1.2	V
VDDS_MMC0	MMC0 IO supply		–0.3	2.2	V
VDDSHV*⁽⁷⁾	Dual Voltage LVCMOS IO supplies	1.8 V	–0.3	2.2	V
VDDSHV*⁽⁷⁾	Dual Voltage LVCMOS IO supplies	3.3 V	–0.3	3.8	V
VPP_CORE VPP MCU	Supply voltage range for EFUSE domains		–0.3	1.89	V
USB0_VBUS⁽⁹⁾	Voltage range for USB VBUS comparator input		–0.3	3.6	V
Steady State Max. Voltage at all fail–safe IO pins		I2C0_SCL, I2C0_SDA, WKUP_I2C0_SCL, WKUP_I2C0_SDA, MCU_I2C0_SCL, MCU_I2C0_SDA, EXTINTn	–0.3	3.8	V
Steady State Max. Voltage at all fail–safe IO pins		MCU_PORz, PORz	–0.3	3.8	V
Steady State Max. Voltage at all other IO pins⁽⁴⁾		VMON1_ER_VSYS⁽⁸⁾, VMON3_IR_VEXT1P8, VMON4_IR_VEXT1P8	–0.3	2.2	V
		VMON2_IR_VCPU	–0.3	1.05	V
		VMON5_IR_VEXT3P3	–0.3	3.8	V
		All other IO pins	–0.3	IO supply voltage + 0.3	V
Transient Overshoot and Undershoot specification at IO pin		20% of IO supply voltage for up to 20% of signal period Figure 7-1 (see IO Transient Voltage Ranges)		0.2 × VDD⁽⁷⁾	V
Latch–up Performance, Class II (125°C)⁽⁵⁾		I–Test	–100	100	mA
Latch–up Performance, Class II (125°C)⁽⁵⁾		Over–Voltage (OV) Test	NA	1.5 × VDD⁽⁷⁾	V
T_STG⁽⁶⁾		Storage temperature	–55	+150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under ^{Recommended Operating
Conditions}. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values are with respect to their associated VSS or VSSA_x, unless otherwise noted.

(7) VDD_* includes: VDD_CORE, VDD_CPU, VDD_MCU, VDD_MCU_WAKE1, VDD_WAKE0
VDDAR_* includes: VDDAR_CORE, VDDAR_CPU, VDDAR_MCU
VDDA_0P8_* includes: VDDA_0P8_CSIRX0_1, VDDA_0P8_CSIRX2, VDDA_0P8_DLL_MMC0, VDDA_0P8_DSITX, VDDA_0P8_DSITX_C, VDDA_0P8_PLL_DDR0, VDDA_0P8_PLL_DDR1, VDDA_0P8_PLL_DDR2, VDDA_0P8_PLL_DDR3, VDDA_0P8_SERDES_C0_1, VDDA_0P8_SERDES_C2, VDDA_0P8_SERDES_C4, VDDA_0P8_SERDES0_1, VDDA_0P8_SERDES2, VDDA_0P8_SERDES4, VDDA_0P8_UFS, VDDA_0P8_USB
VDDA_1P8_* includes: VDDA_1P8_CSIRX0_1, VDDA_1P8_CSIRX2, VDDA_1P8_DSITX, VDDA_1P8_SERDES0_1, VDDA_1P8_SERDES2, VDDA_1P8_SERDES2_4, VDDA_1P8_SERDES4, VDDA_1P8_UFS, VDDA_1P8_USB
VDDA_* includes: VDDA_ADC0, VDDA_ADC1, VDDA_MCU_PLLGRP0, VDDA_MCU_TEMP, VDDA_OSC1, VDDA_PLLGRP0, VDDA_PLLGRP1, VDDA_PLLGRP10, VDDA_PLLGRP12, VDDA_PLLGRP13, VDDA_PLLGRP2, VDDA_PLLGRP5, VDDA_PLLGRP6, VDDA_PLLGRP7, VDDA_PLLGRP8, VDDA_PLLGRP9, VDDA_POR_WKUP, VDDA_TEMP0, VDDA_TEMP1, VDDA_TEMP2, VDDA_TEMP3, VDDA_TEMP4, VDDA_WKUP
VDDS_DDR_* includes: VDDS_DDR, VDDS_DDR_C0, VDDS_DDR_C1, VDDS_DDR_C2, VDDS_DDR_C3
VDDSHV* includes: VDDSHV0, VDDSHV0_MCU, VDDSHV1_MCU, VDDSHV2, VDDSHV2_MCU, VDDSHV5

(4) This parameter applies to all IO pins which are not fail-safe and the requirement applies to all values of IO supply voltage. For example, if the voltage applied to a specific IO supply is 0 volts the valid input voltage range for any IO powered by that supply will be –0.3 to +0.3 volts. Special attention should be applied anytime peripheral devices are not powered from the same power sources used to power the respective IO supply. It is important the attached peripheral never sources a voltage outside the valid input voltage range, including power supply ramp–up and ramp–down sequences.

(5) For current pulse injection:
Pins stressed per JEDEC JESD78E (Class II) and passed with specified I/O pin injection current and clamp voltage of 1.5 times maximum recommended I/O voltage and negative 0.5 times maximum recommended I/O voltage.
For overvoltage performance:
Supplies stressed per JEDEC JESD78E (Class II) and passed specified voltage injection.

(6) For tape and reel the storage temperature range is [–10°C; +50°C] with a maximum relative humidity of 70%. TI recommends returning to ambient room temperature before usage.

(7) VDD is the voltage on the corresponding power-supply pin(s) for the IO.

(8) The VMON_ER_VSYS pin provides a way to monitor the system power supply. For more information, see ^{System Power
Supply Monitor Design Guidelines using VMON/POK}.

(9) An external resistor divider is required to limit the voltage applied to this device pin. For more information, see the ^{USB VBUS Design Guidelines}.

Fail-safe IO terminals are designed such they do not have dependencies on the respective IO power supply voltage. This allows external voltage sources to be connected to these IO terminals when the respective IO power supplies are turned off. The I2C0_SCL, I2C0_SDA, I2C1_SCL, I2C1_SDA, DDR_FS_RESETn, and NMIn are the only fail–safe IO terminals. All other IO terminals are not fail–safe and the voltage applied to them should be limited to the value defined by the Steady State Max. Voltage at all IO pins parameter in ^{Absolute Maximum
Ratings}.

A. T_overshoot + T_undershoot < 20% of T_period

Figure 7-1 IO Transient Voltage Ranges