The FrameValid (FV) and LineValid (LV) indications from the Receive Port indicate approximate frame and line boundaries at the V³Link Receiver input. These signals may not be accurate if the receiver is in CSI-2 input mode and multiple video streams are present at the Receive Port input. A common example of this scenario would be multiple Virtual Channel IDs received on a single port.

When the receiver is in one of the Raw modes the LV and FV provides controls for the video framing. The FV is equivalent to a Vertical Sync (VSYNC) while the LineValid is equivalent to a Horizontal Sync (HSYNC) input to the DVP Mode serializer device (see Section 7.4.27).

The TDES954 allows setting the polarity of these signals by register programming. The FV and LV polarity are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C.

To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register 0xBC. Because the measurement is in V³Link clocks, the minimum FrameValid setup to LineValid timing at the Serializer will vary based on the RAW input operating mode.

A minimum FV to LV timing is required when processing RAW video frames at the serializer input. If the FV to LV minimum setup is not met (by default), the first video line is discarded. Optionally, a register control (PORT_CONFIG:DISCARD_1ST_ON_ERR) forwards the first video line missing some number of pixels at the start of the line.

For other settings of FV_MIN_TIME, the required FV to LV setup in Serializer PCLKs can be determined by:

Absolute Min + (FV_MIN_TIME × Conversion factor)

The minimum LV to FV timing requirement for all RAW modes is 0. See Table 7-11 for the exact timing in Serializer PCLKs.