The TDES954 is designed to support the Power-over-Coax (PoC) method of powering remote sensor systems. With this method, the power is delivered over the same medium (a coaxial cable) used for high-speed digital video data and bidirectional control and diagnostics data transmission. The method uses passive networks or filters that isolate the transmission line from the loading of the DC/DC regulator circuits and their connecting power traces on both sides of the link as shown in Figure 8-1.

Figure 8-1 Power Over Coax (PoC) System Diagram

The PoC networks' impedance of ≥ 1 kΩ over a specific frequency band is recommended to isolate the transmission line from the loading of the regulator circuits. Higher PoC network impedance will contribute to favorable insertion loss and return loss characteristics in the high-speed channel. The lower limit of the frequency band is defined as ½ of the frequency of the bidirectional control channel, f_BCC. The upper limit of the frequency band is the frequency of the forward high-speed channel, f_FC. However, the main criteria that need to be met in the total high-speed channel, which consists of a serializer PCB, a deserializer PCB, and a cable, are the insertion loss and return loss limits defined in the Total Channel Requirements, while the system is under maximum current load and extreme temperature conditions⁽¹⁾⁽²⁾.

Figure 8-2 shows a PoC network recommended for a 4G V³Link consisting of TSER953 and TDES954 pair with the bidirectional channel operating at 50 Mbps (½ f_BCC = 25 MHz) and the forward channel operating at 4.16 Gbps (f_FC ≈ 2.1 GHz).

Figure 8-2 Typical PoC Network for a 4G V³Link

Table 8-1 lists essential components for this particular PoC network.

Figure 8-3 shows a PoC network recommended for a 2G V³Link consisting of a DVP Mode serializer and TDES954 with the bidirectional channel operating at the data rate of 5 Mbps (½ f_BCC = 2.5 MHz) and the forward channel operating at the data rate as high as 1.87 Gbps (f_FC ≈ 1 GHz).

Figure 8-3 Typical PoC Network for a 2G V³Link

Table 8-2 lists essential components for this particular PoC network.

Application report Sending Power over Coax in DS90UB913A Designs (SNLA224) discusses defining PoC networks in more detail.

In addition to the PoC network components selection, their placement and layout play a critical role as well.

• Place the smallest component, typically a ferrite bead or a chip inductor, as close to the connector as possible. Route the high-speed trace through one of its pads to avoid stubs.
• Use the smallest component pads as allowed by manufacturer's design rules. Add anti-pads in the inner planes below the component pads to minimize impedance drop.
• Consult with connector manufacturer for optimized connector footprint. If the connector is mounted on the same side as the IC, minimize the impact of the through-hole connector stubs by routing the high-speed signal traces on the opposite side of the connector mounting side.
• Use coupled 100-Ω differential signal traces from the device pins to the AC-coupling caps. Use 50-Ω single-ended traces from the AC-coupling capacitors to the connector.
• Terminate the inverting signal traces close to the connectors with standard 49.9-Ω resistors.

The suggested characteristics for single-ended PCB traces (microstrips or striplines) for serializer or deserializer boards are detailed in Table 8-3. The effects of the PoC networks must be accounted for when testing the traces for compliance to the suggested limits.

The V_POC noise must be kept to 10 mVp-p or lower on the source / deserializer side of the system. The V_POC fluctuations on the serializer side, caused by the transient current draw of the sensor and the DC resistance of cables and PoC components, must be kept at minimum as well. Increasing the V_POC voltage and adding extra decoupling capacitance (> 10 µF) help reduce the amplitude and slew rate of the V_POC fluctuations.