ZHCSNJ7A April 2021 – February 2023 TDES954
PRODUCTION DATA
The general configuration register enables and disables high level block functionality.
| BIT | FIELD | TYPE | DEFAULT | DESCRIPTION |
|---|---|---|---|---|
| 7:6 | RESERVED | R/W | 0x0 | Reserved |
| 5 | I2C_CONTROLLER _ENABLE | R/W | 0x0 | I2C Controller Enable. This bit must be set if system requires the deserializer to act as proxy controller for remote I2C access to the local I2C bus from remote serializers. 0: Block proxy Controller access to local I2C from remote serializers 1: Enable proxy Controller access to local I2C from remote serializers |
| 4 | OUTPUT_EN_MODE | R/W | 0x1 | Output Enable Mode. If set to 0, the CSI TX output port will be forced to the high-impedance state if no assigned RX ports have an active Receiver lock. If set to 1 and no assigned RX ports have an active Receiver lock the CSI TX output port will continue in normal operation and enter the LP-11 state. CSI TX operation will remain under register control via the CSI_CTL register for each port. |
| 3 | OUTPUT_ENABLE | R/W | 0x1 | Output Enable Control (usage dependant on Output Sleep State Select). If OUTPUT_SLEEP_STATE_SEL is set to 1 and OUTPUT_ENABLE is set to 0, the CSI TX outputs will be forced into a high impedance state. |
| 2 | OUTPUT_SLEEP _STATE _SELECT | R/W | 0x1 | OSS Select to control output state when LOCK is low (usage dependant on Output Enable) When OUTPUT_SLEEP _STATE _SELECT is set to 0, the CSI TX outputs will be forced into a HS-0 state. |
| 1 | RX_PARITY _CHECKER _ENABLE | R/W | 0x1 | V3Link Parity Checker Enable 0: Disable 1: Enable |
| 0 | FORCE_REFCLK _DET | R/W | 0x0 | Force indication of external reference clock 0: Normal operation, reference clock detect circuit indicates the presence of an external reference clock 1: Force reference clock to be indicated present |