A valid 23-MHz to 26-MHz reference clock is required on the REFCLK pin 5 for precise frequency operation. The REFCLK frequency defines all internal clock timers, including the back channel rate, I2C timers, CSI-2 data rate, FrameSync signal parameters, and other timing critical internal circuitry. REFCLK input must be continuous. If the REFCLK input does not detect a transition more than 20 µS, this may cause a disruption in the CSI-2 output. REFCLK should be applied to the TDES954 only when the supply rails are above minimum levels (see Section 9.2). At start-up, the TDES954 defaults to an internal oscillator to generate an backup internal reference clock at nominal frequency of 25 MHz ±10%.

The REFCLK LVCMOS input oscillator specifications are listed in Table 7-2.