The Raw modes provide FrameValid (FV) and LineValid (LV) controls for the video framing. The FV is equivalent to a Vertical Sync (VSYNC) while the LineValid is equivalent to a Horizontal Sync (HSYNC) input to the DVP Mode serializer.

The TDES960 allows setting the polarity of these signals by register programming. The FV and LV polarity are controlled on a per-port basis and can be independently set in the PORT_CONFIG2 register 0x7C.

To prevent false detection of FrameValid, FV must be asserted for a minimum number of clocks prior to first video line to be considered valid. The minimum FrameValid time is programmable in the FV_MIN_TIME register 0xBC. Because the measurement is in V3LINK clocks, the minimum FrameValid setup to LineValid timing at the Serializer will vary based on operating mode.

A minimum FV to LV timing is required when processing video frames from a RAW serializer input. If the FV to LV minimum setup is not met (by default), the first video line is discarded. Optionally, a register control (PORT_CONFIG:DISCARD_1ST_ON_ERR) forwards the first video line missing some number of pixels at the start of the line. There is no timing restrictions at the end of the frame.

Figure 7-5 Minimum FV to LV

For other settings of FV_MIN_TIME, use Equation 1 to determine the required FV to LV setup in Serializer PCLKs.

The minimum LV to FV timing requirement for all three RAW modes is 0. See Table 7-12 for the exact timing in Serializer PCLKs.