5 Pin Configuration and Functions

Figure 5-1 RTD Package
64-Pin VQFN
(Top View)

Table 5-1 Pin Functions

PIN		I/O TYPE	DESCRIPTION
NAME	NO.	I/O TYPE	DESCRIPTION
MIPI CSI-2 TX INTERFACE
CSI0_CLKN	22	O	CSI-2 TX Port 0 differential clock output pins. Leave unused pins as No Connect.
CSI0_CLKP	23
CSI0_D0N	24		CSI-2 TX Port 0 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control. Leave unused pins as No Connect.
CSI0_D0P	25
CSI0_D1N	26
CSI0_D1P	27
CSI0_D2N	28
CSI0_D2P	29
CSI0_D3N	30
CSI0_D3P	31
CSI1_CLKN	34	O	CSI-2 TX Port 1 differential clock output pins. Leave unused pins as No Connect.
CSI1_CLKP	35
CSI1_D0N	36		CSI-2 TX Port 1 differential data output pins. Use CSI_PORT_SEL, CSI_CTL, and CSI_CTL2 registers for the CSI-2 TX control. Leave unused pins as No Connect.
CSI1_D0P	37
CSI1_D1N	38
CSI1_D1P	39
CSI1_D2N	40
CSI1_D2P	41
CSI1_D3N	42
CSI1_D3P	43
V³Link RX INTERFACE
RIN0+	50	I/O	V³Link RX Port 0 pins. The port receives V³Link high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible V³Link serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4. If port is unused, set RX_PORT_CTL register bit 0 to 0 to disable RX Port 0 and leave the pins as No Connect.
RIN0-	51
RIN1+	53		V³Link RX Port 1 pins. The port receives V³Link high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible V³Link serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4. If port is unused, set RX_PORT_CTL register bit 1 to 0 to disable RX Port 1 and leave the pins as No Connect.
RIN1-	54
RIN2+	59		V³Link RX Port 2 pins. The port receives V³Link high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible V³Link serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4. If port is unused, set RX_PORT_CTL register bit 2 to 0 to disable RX Port 2 and leave the pins as No Connect.
RIN2-	60
RIN3+	62		V³Link RX Port 3 pins. The port receives V³Link high-speed forward channel video and control data and transmits back channel control data. It can interface with a compatible V³Link serializer TX through a STP or coaxial cable (see Figure 8-6 and Figure 8-7). It must be AC-coupled per Table 8-4. If port is unused, set RX_PORT_CTL register bit 3 to 0 to disable RX Port 3 and leave the pins as No Connect.
RIN3-	63
SYNCHRONIZATION AND GENERAL-PURPOSE I/O
GPIO0	9	I/O, PD	General-Purpose Input/Output pins. The pins can be used to control and respond to various commands. They may be configured to be input signals for the corresponding GPIOs on the serializer or they may be configured to be outputs to follow local register settings. At power up, the GPIO pins are disabled and by default include a pulldown resistor (25-kΩ typ). See Section 7.4.11. for programmability. If unused, leave the pin as No Connect.
GPIO1	10
GPIO2	14
GPIO3	15
GPIO4	17
GPIO5	18
GPIO6	19
GPIO7	20
INTB	6	O, OD	Interrupt Output pin. INTB is an active-low open drain and controlled by the status registers. See Section 7.5.9. Recommend a 4.7-kΩ Pullup to 1.8 V or 3.3 V. If unused, leave the pin as No Connect.
SERIAL CONTROL BUS (I2C)
I2C_SCL	12	I/O, OD	Primary I2C Clock Input / Output interface pin. See Section 7.5.1. Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
I2C_SDA	11	I/O, OD	Primary I2C Data Input / Output interface pin. See Section 7.5.1. Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
I2C_SCL2	8	I/O, OD	Secondary I2C Clock Input / Output interface pin. See Section 7.5.2. Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
I2C_SDA2	7	I/O, OD	Secondary I2C Data Input / Output interface pin. See Section 7.5.2. Refer to "I2C Bus Pullup Resistor Calculation"(SLVA689) to determine the pull-up resistor value to VDDIO. If unused, leave this pin unconnected.
CONFIGURATION AND CONTROL
IDX	46	S	I2C Serial Control Bus Device ID Address Select configuration pin. Connect to an external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 7-17.
MODE	45	S	Mode Select configuration pin. Connect to external pullup to VDD18 and a pulldown to GND to create a voltage divider. See Table 7-1.
PDB	3	I, PD	Inverted Power-Down input pin. Typically connected to a processor GPIO with a pulldown. When PDB input is brought HIGH, the device is enabled and internal registers and state machines are reset to default values. Asserting PDB signal low will power down the device and consume minimum power. The default function of this pin is PDB = LOW; POWER DOWN with an internal 50-kΩ internal pulldown enabled. PDB must remain low until after power supplies are applied and reach minimum required levels. See Section 8.4.1. INPUT IS 3.3-V TOLERANT PDB = 1.8 V, device is enabled (normal operation) PDB = 0 V, device is powered down.
POWER AND GROUND
VDDIO	16	P	1.8-V (±5%) OR 3.3-V (±10%) LVCMOS I/O Power Requires 1-μF and 0.1-μF or 0.01-μF capacitors to GND.
VDD_CSI0 VDD_CSI1	21 33	P	1.1-V (±5%) Power Supplies Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF and 10-μF decoupling is recommended for the pin group.
VDDL1 VDDL2	13 44	P	1.1-V (±5%) Power Supplies Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF and 10-μF decoupling is recommended for the pin group.
VDD_FPD1 VDD_FPD2	52 61	P	1.1-V (±5%) Power Supplies Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF and 10-μF decoupling is recommended for the pin group.
VDD18_P3 VDD18_P2 VDD18_P1 VDD18_P0	1 2 47 48	P	1.8-V (±5%) Power Supplies Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF, and 10-μF decoupling is recommended for the pin group.
VDD18A	32	P	1.8-V (±5%) Power Supplies Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF, and 10-μF decoupling is recommended for the pin group.
VDD18_FPD0 VDD18_FPD1 VDD18_FPD2 VDD18_FPD3	49 55 58 64	P	1.8-V (±5%) Power Supplies Requires 0.1-μF or 0.01-μF capacitors to GND at each VDD pin. Additional 1-μF, and 10-μF decoupling is recommended for the pin group.
GND	DAP	G	DAP is the large metal contact at the bottom side, located at the center of the VQFN package. Connect to the ground plane (GND).
OTHERS
REFCLK	5	I	Reference clock oscillator input. Typically connected to a 23-MHz to 26-MHz LVCMOS-level oscillator (100 ppm). For 400-Mbps, 800-Mbps, 1.2-Gbps or 1.6-Gbps CSI-2 data rates, use 25-MHz frequency. For the oscillator requirements, see Section 7.4.4. For other common CSI-2 data rates, see Section 7.4.19.
RES	4	-	This pin must be tied to GND for normal operation.
CMLOUTP	56	O	Channel Monitor Loop-through Driver differential output. Route to a test point or a pad with 100-Ω termination resistor between pins for channel monitoring (recommended). See Section 7.4.8.
CMLOUTN	57	O

The definitions below define the functionality of the I/O cells for each pin. TYPE:

I = Input
O = Output
I/O = Input/Output
S = Strap Input
PD = Internal Pulldown
OD = Open Drain
P = Power Supply
G = Ground