ZHCSFY1F December 2016 – April 2024 TDP158
PRODUCTION DATA
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| LANE_SWAP | Lane Control | DP-Mode | SIG_EN | PD_EN | HPD_AUTO_PWRDWN_DISABLE | I2C_DR_CTL | |
| R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W |
| LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
| Bit | Field | Type | Default | Description |
|---|---|---|---|---|
| 7 | LANE_SWAP | R/W | 1’b0 | This field Swaps the input lanes as per Figure 7-4 and Section 7.3.4 and valid when in HDMI mode only. 0 − Disable (default) No Lane Swap 1 − Enable: Swaps both Input and Output Lanes |
| 6 | Lane Control | R/W | 1’b0 | See Section 7.3.3 0 – Global (Default) 1 – Independent Note: In default mode reg0C and reg0D control all lanes. When set to 1 each lane can be individually controlled for Swing, EQ, Pre-emphasis. |
| 5 | DP-Mode | R/W | 1’b0 | See Section 7.3.12 0 – Normal DP158 Operation (Default) 1 – All lanes behave as data lanes and full control through I2C only |
| 4 | SIG_EN | R/W | 1’b1 | This field enables the clock lane activity detect
circuitry. See Section 7.3.7 0 – Disable Clock detector circuit closed and receiver always works in normal operation. 1 – Enable (default), Clock detector circuit will make the receiver automatically enter the standby state when no valid data detect. |
| 3 | PD_EN | R/W | 1’b0 | 0 – Normal working (default) 1 – Forced Power down by I2C, Lowest Power state |
| 2 | HPD_AUTO_PWRDWN_DISABL | R/W | 1’b0 | 0 – Automatically enters Power Down mode based on HPD_SNK
(default) 1 – Will not automatically enter Power Down mode |
| 1:0 | I2C_DR_CTL | R/W | 2’b10 | I2C data rate supported for configuring device. 00 – 5Kbps 01 – 10Kbps 10 – 100Kbps( Default ) 11 – 400Kbps |