ZHCSFY1F December   2016  – April 2024 TDP158

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics, Power Supply
    6. 5.6  Electrical Characteristics, Differential Input
    7. 5.7  Electrical Characteristics, TMDS Differential Output
    8. 5.8  Electrical Characteristics, DDC, I2C, HPD, and ARC
    9. 5.9  Electrical Characteristics, TMDS Differential Output in DP-Mode
    10. 5.10 Switching Characteristics, TMDS
    11. 5.11 Switching Characteristics, HPD
    12. 5.12 Switching Characteristics, DDC and I2C
    13. 5.13 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reset Implementation
      2. 7.3.2  Operation Timing
      3. 7.3.3  Lane Control
      4. 7.3.4  Swap
      5. 7.3.5  Main Link Inputs
      6. 7.3.6  Receiver Equalizer
      7. 7.3.7  Input Signal Detect Block
      8. 7.3.8  Transmitter Impedance Control
      9. 7.3.9  TMDS Outputs
      10. 7.3.10 Slew Rate Control
      11. 7.3.11 Pre-Emphasis
      12. 7.3.12 DP-Mode Description
    4. 7.4 Device Functional Modes
      1. 7.4.1 DDC Training for HDMI 2.0 Data Rate Monitor
      2. 7.4.2 DDC Functional Description
    5. 7.5 Register Maps
      1. 7.5.1  Local I2C Control BIT Access TAG Convention
      2. 7.5.2  BIT Access Tag Conventions
      3. 7.5.3  CSR Bit Field Definitions, DEVICE_ID (address = 00h≅07h)
      4. 7.5.4  CSR Bit Field Definitions, REV_ID (address = 08h )
      5. 7.5.5  CSR Bit Field Definitions – MISC CONTROL 09h (address = 09h)
      6. 7.5.6  CSR Bit Field Definitions – MISC CONTROL 0Ah (address = 0Ah)
      7. 7.5.7  CSR Bit Field Definitions – MISC CONTROL 0Bh (address = 0Bh)
      8. 7.5.8  CSR Bit Field Definitions – MISC CONTROL 0Ch (address = 0Ch)
      9. 7.5.9  CSR Bit Field Definitions, Equalization Control Register (address = 0Dh)
      10. 7.5.10 CSR Bit Field Definitions, POWER MODE STATUS (address = 20h)
      11. 7.5.11 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 30h)
      12. 7.5.12 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 31h)
      13. 7.5.13 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 32h)
      14. 7.5.14 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 33h)
      15. 7.5.15 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 34h)
      16. 7.5.16 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 35h)
      17. 7.5.17 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Dh)
      18. 7.5.18 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Eh)
      19. 7.5.19 CSR Bit Field Definitions, DP-Mode and INDIVIDUAL LANE CONTROL (address = 4Fh)
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Source Side
        2. 8.2.2.2 DDC Pull Up Resistors
      3. 8.2.3 Application Curves
      4. 8.2.4 Application with DDC Snoop
        1. 8.2.4.1 Source Side HDMI Application
      5. 8.2.5 9.1.2 Source Side HDMI /DP Application Using DP-Mode
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Management
      2. 8.3.2 Standby Power
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 接收文档更新通知
    3. 9.3 支持资源
    4. 9.4 Trademarks
    5. 9.5 静电放电警告
    6. 9.6 术语表
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

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7.3.11 Pre-Emphasis

The TDP158 provides pre-emphasis on the data lanes allowing the output signal pre-conditioning to offset interconnect losses between the TDP158 outputs and a TMDS receiver. Pre-emphasis is not implemented on the clock lane unless the TDP158 is in DP mode; at which time, it becomes a data lane. The default value for pre-emphasis is 0dB. There are two methods to implement pre-emphasis, pin strapping or through I2C programming. When using pin strapping, the SDA_CTL/PRE pin controls global pre-emphasis values of 0dB or 3.5dB. Through I2C, reg0Ch[1:0] pre-emphasis values are 0dB, 3.5dB, and 6dB. The 6dB value has different meanings when the device is in normal operational mode (reg09h[5] = 0) or when the TDP158 has been put into DP-mode (reg09h[5] = 1). As Figure 7-6 shows, the 6dB pre-emphasis setting will result in an output of 3dB of pre-emphasis with 3dB of de-emphasis when device is in normal HDMI operation. As Figure 7-7 shows, the output will be about 5dB pre-emphasis with a 1dB de-emphasis when selecting 6dB pre-emphasis setting for DP-mode. VOD(PP) value will not go above 1V.

GUID-E6F0CA5A-5847-47EE-9237-5D1E70789BAE-low.gifFigure 7-6 6dB Pre-Emphasis Setting in Normal Operation
GUID-FC90D731-2905-427F-B780-C0F19A905C2F-low.gifFigure 7-7 6dB Pre-Emphasis in DP-Mode
Table 7-5 Swing and Pre-Emphasis Programming Based Upon 6kΩ VSADJ Resistor
Global ControlIndependent Lane Control
ModeReg09h[6]
Lane CTL		Reg09[5]
Mode CTL		P0_Reg0C[7:0]Reg09h[6]
Lane CTL		Reg09[5]
Mode CTL		P0_Reg0C[7:0]
HDMI 008’h00108’h00
DP SWG0, PRE0018’h80118’h80
DP SWG0, PRE1018’hC1118’hC1
DP SWG0, PRE2018’h42118’h42
DP SWG1, PRE0018’hC0118’hA0
DP SWG1, PRE1018’hF1118’h21
DP SWG1, PRE2018’h52118’h62
DP SWG2, PRE0018’h20118’h00
DP SWG2, PRE1018’h51118’h61
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